14. Direct Memory Access Controller (DMAC)

Rev.1.00 Jan. 10, 2008 Page 725 of 1658

REJ09B0261-0100

Acceptance started
Accepted after one cycle of CLKOUT
after the end of the first of the multiple bus cycles
1st acceptance 2nd acceptance
: Non-sensitive period
Acceptance started
Accepted after one cycle of CLKOUT
at the rising edge of DACK
1st acceptance 2nd acceptance
Bus cycle
DREQ
(
Overrun 0, High level)
DRAK (High-active)
DACK (High-active)
Bus cycle
DREQ
(
Overrun 1, High level)
DRAK (High-active)
DACK (High-active)
CLKOUT
Address
CPU CPU
DMAC
CLKOUT
Address
CPU CPUDMAC
Figure 14.18 Example 3 of DREQ Input Detection in Cycle Steal Mode Level Detection (Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, or 16/32-Byte Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Is Connected)

CLKOUT

CPU DMAC DMAC
Burst acceptance
: Non-sensitive period

Bus cycle

DREQ

(Rising edge)

DRAK

(High-active)

DACK

(High-active)

Figure 14.19 Example of DREQ Input Detection in Burst Mode Edge Detection