Performance Tests

a.C￿￿￿k t￿￿ s￿￿￿a￿ ￿￿v￿￿s:

￿Contact the oscilloscope probe to the pins on 2 X13 header (see Figure 4122). Check that the oscilloscope display shows these signals:

￿Data signals D01D11 and CLK (Clock) are TTL level output.

￿All other pins are ground.

2X13 Header

CLK

D11

GND

D1

D0

GND

Digital Data Out Cable

Figure 4￿22:￿Output Pins on the Digital Data Out Cable

4.C￿￿￿k t￿￿ CH2 ￿￿￿￿ta￿ ￿ata ￿ut￿ut s￿￿￿a￿s:

a.C￿a￿￿￿ ￿￿￿￿￿￿t￿￿￿: Change the connection for the digital data out cable from CH1 DIGITAL DATA OUT connector to CH2 DIGITAL DATA OUT connector.

b.Repeat the step 2 and 3 to check the CH2 digital data output sig1 nals.

5.￿ur￿ ￿￿￿ ￿qu￿￿￿￿￿t ￿ut￿ut a￿￿ ￿￿s￿￿￿￿￿￿t t￿st ￿￿￿ku￿:

a.D￿sab￿￿ ￿￿w￿r su￿￿￿y ￿ut￿ut: Turn off power supply output.

b.R￿￿￿v￿ ￿￿￿￿￿￿t￿￿￿s: Disconnect all connections to the AWG2005.

4￿48

Performance Verification