2 Troubleshooting Procedures | 2.4 System Board Troubleshooting |
Table
LED Status | Test item | Message |
|
|
|
FFh | Start | Register initialization for boot block |
|
|
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B0h | Flash ROM check | PIT ch.0 initialization |
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|
|
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| BIOS rewrite flag initialization |
|
|
|
|
| Transition to protected mode |
|
|
|
|
| Boot block checksum |
|
|
|
|
| Checksum check except boot block |
|
|
|
B1h | EC/KBC rewrite check | KBC initialization |
|
|
|
B2h | BIOS rewrite check | BIOS rewrite request check |
|
|
|
B3h | System BIOS rewrite | System BIOS rewrite transition to IRT |
| transition to IRT |
|
| BIOS rewrite process | BIOS rewrite register initialization |
|
|
|
|
| PIT channel 1 initialization |
|
|
|
|
| PIT, DMAC,PIC initialization |
|
|
|
|
| Memory type check |
|
|
|
|
| Cache bus, L2 initialization, configuration |
|
|
|
|
| Enabling L1 cache |
|
|
|
|
| Memory clear |
|
|
|
|
| Protecting flash ROM area cache |
|
|
|
B7h | FDC interruption | Enabling FDC interruption |
|
|
|
|
| HW debug |
|
|
|
|
| Display initialization |
|
|
|
B8h | Sound control initialization | Sound controller initialization (for beep) |
|
|
|
|
| Message display |
|
|
|
|
| Key input |
|
|
|
|
| Reading CHGBIOS.EXE |
|
|
|
00h | IRT Check system | IRT Check system |
|
|
|
|
| Protecting cache |
|
|
|
|
| Special register, Intel® chip set initialization |
|
| PIT channel 1 initialization |
|
|
|
01h | Memory check | DRAM type and size check |
|
|
|
02h | ||
|
|
|
03h | CMOS check and | Enabling L1 cache |
| initialization |
|
| CMOS access test | |
|
| |
|
|
|
Satellite Pro M10 Series Maintenance Manual |
