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Freescale Semiconductor MCF51QE128RM Manual
424 pages 4.75 Mb
3 MCF51QE128 Series Features5 7 Contents23 Chapter 1 Device Overview43 Chapter 3 Modes of Operation57 Chapter 4 Memory93 Chapter 5 Resets, Interrupts, and General System Control5.1 Introduction 5.2 Features 5.3 Microcontroller Reset 95 5.4 Interrupts and Exceptions5.4.1 External Interrupt Request (IRQ) Pin5.4.1.1 Pin Configuration Options 5.4.1.2 Edge and Level Sensitivity 5.4.1.3 External Interrupt Initialization 96 5.5 Low-Voltage Detect (LVD) System5.5.1 Power-On Reset Operation 5.5.2 LVD Reset Operation 5.5.3 LVD Interrupt Operation 5.5.4 Low-Voltage Warning (LVW) Interrupt Operation 97 5.6 Peripheral Clock Gating5.7 Reset, Interrupt, and System Control Registers and Control Bits 113 Chapter 6 Parallel Input/Output Control6.1 Port Data and Data Direction 114 6.2 Pull-up, Slew Rate, and Drive Strength6.2.1 Port Internal Pull-up Enable 6.2.2 Port Slew Rate Enable 6.2.3 Port Drive Strength Select 115 6.3 Port Data Set, Clear and Toggle Data Registers6.3.1 Port Data Set Registers 6.3.2 Port Data Clear Registers 6.3.3 Port Data Toggle Register 116 6.4 V1 ColdFire Rapid GPIO Functionality6.5 Keyboard Interrupts 118 6.6 Pin Behavior in Stop Modes6.7 Parallel I/O, Keyboard Interrupt, and Pin Control Registers6.7.1 Port A Registers119 6.7.1.1 Port A Data Register (PTAD)6.7.1.2 Port A Data Direction Register (PTADD) 6.7.1.3 Port A Pull Enable Register (PTAPE)Figure 6-4. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Figure 6-5. Port A Data Direction Register (PTADD) Table 6-2. PTADD Register Field Descriptions 120 6.7.1.4 Port A Slew Rate Enable Register (PTASE)6.7.1.5 Port A Drive Strength Selection Register (PTADS)Figure 6-8. Drive Strength Selection for Port A Register (PTADS) 121 6.7.2 Port B RegistersPort B is controlled by the registers listed below.Figure 6-10. Port B Data Direction Register (PTBDD) 6.7.2.2 Port B Data Direction Register (PTBDD) 6.7.2.1 Port B Data Register (PTBD)Table6-5. PTADS Register Field Descriptions Figure 6-9. Port B Data Register (PTBD) Table6-6. PTBD Register Field Descriptions 122 6.7.2.3 Port B Pull Enable Register (PTBPE)6.7.2.4 Port B Slew Rate Enable Register (PTBSE)Table 6-7. PTBDD Register Field Descriptions 6.7.2.5 Port B Drive Strength Selection Register (PTBDS) 123 6.7.3 Port C Registers6.7.3.1 Port C Data Register (PTCD)Port C is controlled by the registers listed below.Figure 6-14. Port C Data Register (PTCD) Table 6-11. PTCD Register Field Descriptions 124 6.7.3.2 Port C Data Direction Register (PTCDD)6.7.3.3 Port C Data Set Register (PTCSET)Figure 6-17. Port C Data Clear Register (PTCCLR) 6.7.3.4 Port C Data Clear Register (PTCCLR)Figure 6-15. Port C Data Direction Register (PTCDD) Table 6-12. PTCDD Register Field Descriptions Figure 6-16. Port C Data Set Register (PTCSET) Table 6-13. PTCSET Register Field Descriptions 125 6.7.3.5 Port C Toggle Register (PTCTOG)6.7.3.6 Port C Pull Enable Register (PTCPE)Table 6-14. PTCCLR Register Field Descriptions Figure 6-18. Port C Toggle Enable Register (PTCTOG) Table 6-15. PTCTOG Register Field Descriptions 6.7.3.7 Port C Slew Rate Enable Register (PTCSE) 6.7.3.8 Port C Drive Strength Selection Register (PTCDS)Figure 6-22. Port D Data Register (PTDD) 6.7.4.1 Port D Data Register (PTDD) 126 6.7.4 Port D RegistersPort D is controlled by the registers listed below. 127 6.7.4.2 Port D Data Direction Register (PTDDD)6.7.4.3 Port D Pull Enable Register (PTDPE)Table 6-19. PTDD Register Field Descriptions Figure 6-23. Port D Data Direction Register (PTDDD) Table 6-20. PTDDD Register Field Descriptions 6.7.4.4 Port D Slew Rate Enable Register (PTDSE) 6.7.4.5 Port D Drive Strength Selection Register (PTDDS)Figure 6-27. Port E Data Register (PTED) 6.7.5.1 Port E Data Register (PTED) 128 6.7.5 Port E RegistersPort E is controlled by the registers listed below. 129 6.7.5.2 Port E Data Direction Register (PTEDD)6.7.5.3 Port E Data Set Register (PTESET)Table 6-24. PTED Register Field Descriptions Figure 6-28. Port E Data Direction Register (PTEDD) Table 6-25. PTEDD Register Field Descriptions Figure 6-29. Port E Data Set Register (PTESET) Table 6-26. PTESET Register Field Descriptions 130 6.7.5.4 Port E Data Clear Register (PTECLR)6.7.5.5 Port E Toggle Register (PTETOG)Figure 6-32. Internal Pull Enable for Port E Register (PTEPE) 6.7.5.6 Port E Pull Enable Register (PTEPE)Figure 6-30. Port E Data Clear Register (PTECLR) Table 6-27. PTECLR Register Field Descriptions Figure 6-31. Port E Toggle Enable Register (PTETOG) Table 6-28. PTETOG Register Field Descriptions 131 6.7.5.7 Port E Slew Rate Enable Register (PTESE)6.7.5.8 Port E Drive Strength Selection Register (PTEDS)Table 6-29. PTEPE Register Field Descriptions 132 6.7.6 Port F RegistersPort F is controlled by the registers listed below. 6.7.6.1 Port F Data Register (PTFD) 6.7.6.2 Port F Data Direction Register (PTFDD) 6.7.6.3 Port F Pull Enable Register (PTFPE)Figure 6-35. Port F Data Register (PTFD) Table 6-32. PTFD Register Field Descriptions Figure 6-36. Port F Data Direction Register (PTFDD) Table 6-33. PTFDD Register Field Descriptions 133 6.7.6.4 Port F Slew Rate Enable Register (PTFSE)6.7.6.5 Port F Drive Strength Selection Register (PTFDS)Figure 6-39. Drive Strength Selection for Port F Register (PTFDS) 134 6.7.7 Port G RegistersPort G is controlled by the registers listed below. 6.7.7.2 Port G Data Direction Register (PTGDD) 6.7.7.1 Port G Data Register (PTGD)Table 6-36. PTFDS Register Field Descriptions Figure 6-40. Port G Data Register (PTGD) Table 6-37. PTGD Register Field Descriptions Figure 6-41. Port G Data Direction Register (PTGDD) Table 6-38. PTGDD Register Field Descriptions 135 6.7.7.3 Port G Pull Enable Register (PTGPE)Figure 6-44. Drive Strength Selection for Port G Register (PTGDS) 6.7.7.5 Port G Drive Strength Selection Register (PTGDS) 6.7.7.4 Port G Slew Rate Enable Register (PTGSE) 136 6.7.8 Port H RegistersPort H is controlled by the registers listed below. 6.7.8.2 Port H Data Direction Register (PTHDD) 6.7.8.1 Port H Data Register (PTHD)Table 6-41. PTGDS Register Field Descriptions Figure 6-45. Port H Data Register (PTHD) Table 6-42. PTHD Register Field Descriptions Figure 6-46. Port H Data Direction Register (PTHDD) Table 6-43. PTHDD Register Field Descriptions 137 6.7.8.3 Port H Pull Enable Register (PTHPE)Figure 6-49. Drive Strength Selection for Port H Register (PTHDS) 6.7.8.5 Port H Drive Strength Selection Register (PTHDS) 6.7.8.4 Port H Slew Rate Enable Register (PTHSE) 138 6.7.9 Port J RegistersPort J is controlled by the registers listed below. 6.7.9.2 Port J Data Direction Register (PTJDD) 6.7.9.1 Port J Data Register (PTJD)Table 6-46. PTHDS Register Field Descriptions Figure 6-50. Port J Data Register (PTJD) Table 6-47. PTJD Register Field Descriptions Figure 6-51. Port J Data Direction Register (PTJDD) Table 6-48. PTJDD Register Field Descriptions 139 6.7.9.3 Port J Pull Enable Register (PTJPE)Figure 6-54. Drive Strength Selection for Port J Register (PTJDS) 6.7.9.5 Port J Drive Strength Selection Register (PTJDS) 6.7.9.4 Port J Slew Rate Enable Register (PTJSE) 140 6.7.10 Keyboard Interrupt 1 (KBI1) Registers6.7.10.1 KBI1 Interrupt Status and Control Register (KBI1SC)Table 6-51. PTJDS Register Field Descriptions Table 6-52. KBI1 Pin Mapping 6.7.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) 6.7.10.3 KBI1 Interrupt Edge Select Register (KBI1ES) 141 6.7.11 Keyboard Interrupt 1 (KBI2) Registers 145 Chapter 7 ColdFire Core173 Chapter 8 Interrupt Controller (CF1_INTC)193 Chapter 9 Rapid GPIO (RGPIO)207 Chapter 10 Analog Comparator 3V (ACMPVLPV1)10.1 Introduction10.1.1 ACMP Configuration Information 10.1.2 ACMP/TPM Configuration Information 10.1.3 ACMP Clock Gating 211 10.1.5 Features10.1.6 Modes of Operation 10.1.6.1 Wait Mode Operation 10.1.6.2 Stop3 Mode Operation 10.1.6.3 Stop2 Mode Operation 10.1.6.4 Active Background Mode Operation 10.1.7 Block DiagramFigure 10-2. Analog Comparator Module Block Diagram 212 10.2 External Signal Description10.3 Register Definition10.3.1 Status and Control Register (ACMPxSC)Figure 10-3. ACMP Status and Control Register (ACMPxSC) + 213 10.4 Functional Description10.5 InterruptsTable 10-1. ACMPxSC Field Descriptions 215 Chapter 11 Analog-to-Digital Converter (S08ADC12V1)243 Chapter 12 Internal Clock Source (S08ICSV3)12.1 Introduction12.1.1 External Oscillator 12.1.2 Stop2 Mode Considerations 247 12.1.3 Features248 12.1.4 Block DiagramFigure 12-2 is the ICS block diagram.Figure 12-2. Internal Clock Source (ICS) Block Diagram 12.1.5 Modes of OperationThere are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. 12.1.5.1 FLL Engaged Internal (FEI) 12.1.5.2 FLL Engaged External (FEE) 12.1.5.3 FLL Bypassed Internal (FBI) 12.1.5.4 FLL Bypassed Internal Low Power (FBILP) 12.1.5.5 FLL Bypassed External (FBE) 12.1.5.6 FLL Bypassed External Low Power (FBELP) 12.1.5.7 Stop (STOP) 249 12.2 External Signal Description12.3 Register Definition 254 12.4 Functional Description12.4.1 Operational ModesFigure 12-7. Clock Switching Modes 12.4.1.1 FLL Engaged Internal (FEI) 255 12.4.1.2 FLL Engaged External (FEE)12.4.1.3 FLL Bypassed Internal (FBI) 12.4.1.4 FLL Bypassed Internal Low Power (FBILP) 12.4.1.5 FLL Bypassed External (FBE) 12.4.1.6 FLL Bypassed External Low Power (FBELP) 12.4.1.7 Stop 256 12.4.2 Mode Switching12.4.3 Bus Frequency Divider 257 12.4.4 Low Power Bit Usage12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator 12.4.6 Internal Reference Clock 12.4.7 External Reference Clock 259 Chapter 13 Inter-Integrated Circuit (S08IICV2)13.1 Introduction13.1.1 Module Configuration 13.1.2 Interrupt Vectors 262 13.1.3 Features13.1.4 Modes of OperationFreescale Semiconductor 2-263 13.1.5 Block DiagramFigure 13-2 is a block diagram of the IIC. This section consists of the IIC register descriptions in address order. Figure 13-2. IIC Functional Block Diagram 263 13.2 External Signal DescriptionThis section describes each user-accessible pin signal. 13.2.1 SCL Serial Clock LineThe bidirectional SCL is the serial clock line of the IIC system. 13.2.2 SDA Serial Data LineThe bidirectional SDA is the serial data line of the IIC system. 13.3 Register Definition 270 13.4 Functional Description13.4.1 IIC Protocol 274 13.4.2 10-bit Address13.4.2.1 Master-Transmitter Addresses a Slave-Receiver 13.4.2.2 Master-Receiver Addresses a Slave-Transmitter 13.4.3 General Call Address 275 13.5 Resets13.6 Interrupts13.6.1 Byte Transfer Interrupt 13.6.2 Address Detect Interrupt 13.6.3 Arbitration Lost Interrupt 277 13.7 Initialization/Application Information281 Chapter 14 Real-Time Counter (S08RTCV1)14.1 Introduction14.1.1 ADC Hardware Trigger 14.1.2 RTC Clock Sources 14.1.3 RTC Modes of Operation14.1.3.1 RTC Status after Stop2 Wakeup 14.1.3.2 Clocks in Stop Modes 14.1.4 RTC Clock Gating 284 14.1.6 Features14.1.7 Modes of Operation14.1.7.1 Wait Mode 14.1.7.2 Stop Modes 14.1.7.3 Active Background Mode 14.1.8 Block Diagram The block diagram for the RTC module is shown in Figure 14-1. Figure 14-1. Real-Time Counter (RTC) Block Diagram 285 14.2 External Signal DescriptionThe RTC does not include any off-chip signals. 14.3 Register DefinitionTable 14-1. RTC Register Summary 286 14.3.1 RTC Status and Control Register (RTCSC) Figure 14-2. RTC Status and Control Register (RTCSC) Table 14-2. RTCSC Field Descriptions Table 14-3. RTC Prescaler Divide-by values 14.3.2 RTC Counter Register (RTCCNT) 14.3.3 RTC Modulo Register (RTCMOD) 287 14.4 Functional Description289 14.5 Initialization/Application Information291 Chapter 15 Serial Communications Interface (S08SCIV4)313 Chapter 16 Serial Peripheral Interface (S08SPIV3)331 Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3)355 Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)421 Appendix A Revision HistoryA.1 Changes between Rev. 2 and Rev. 3
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