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Freescale Semiconductor MCF51QE128RM Configuration/Status Register 2 CSR2, CSR2 Reference Summary

Models: MCF51QE128RM

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					Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
	Table 18-7. XCSR Field Descriptions (continued)

Field				Description

2–1	Automatic PC synchronization control. Determines the periodic interval of PC address captures, if
APCSC	XCSR[APCENB] is set. When the selected interval is reached, a SYNC_PC command is sent to the ColdFire
	CPU. For more information on the SYNC_PC operation, see the APCENB description.
	The chosen frequency depends on CSR2[APCDIV16] as shown in the equation and table below:
				2(APCSC + 1) × 1024				Eqn. 18-1
		PC address capture period = ----------------------------------------------------------						Eqn. 18-1
				16APCDIV16
		XCSR	CSR2	XCSR		SYNC_PC Interval
		[APCENB]	[APCDIV16]	[APCSC]		SYNC_PC Interval
		[APCENB]	[APCDIV16]	[APCSC]

		1	0	00		2048 cycles

		1	0	01		4096 cycles

		1	0	10		8192 cycles

		1	0	11		16384 cycles

		1	1	00		128 cycles

		1	1	01		256 cycles

		1	1	10		512 cycles

		1	1	11		1024 cycles


0	Automatic PC synchronization enable. Enables the periodic output of the PC which can be used for PST/DDATA
APCENB	trace synchronization.
	As described in XCSR[APCSC], when the enabled periodic timer expires, a SYNC_PC command is sent to the
	ColdFire CPU which generates a forced instruction fetch of the next instruction. The PST/DDATA module captures
	the target address as defined by CSR[9] (two bytes if CSR[9] is cleared, three bytes if CSR[9] is set). This
	produces a PST sequence of 0x5 (indicating a taken branch), followed by the PST marker indicating a 2- or 3-byte
	address, and then the captured instruction address.
	0 Automatic PC synchronization disabled
	1 Automatic PC synchronization enabled

18.3.3Configuration/Status Register 2 (CSR2)

The 32-bit CSR2 is partitioned into two sections. The upper byte contains status and configuration bits always accessible to the BDM interface, even if debug mode is disabled. The lower 24 bits contain fields related to the configuration of the PST trace buffer (PSTB).

There are multiple ways to reference CSR2. They are summarized in Table 18-8.

Table 18-8. CSR2 Reference Summary

Method	Reference Details

READ_CSR2_BYTE	Reads CSR2[31–24] from the BDM interface. Available in all modes.

WRITE_CSR2_BYTE	Writes CSR2[31–24] from the BDM interface. Available in all modes.

READ_DREG	Reads CSR2[31–0] from the BDM interface. Classified as a non-intrusive BDM command.

	MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual Configuration/Status Register 2 CSR2, CSR2 Reference Summary, Xcsr CSR2

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MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Freescale Semiconductor Chapter Resets, Interrupts, and General System ControlTitle Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Chapter Inter-Integrated Circuit S08IICV2 Section Number TitleReal-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History Devices in the MCF51QE128/64/32 Series MCF51QE128 Series Features by MCU and PackageFeature MCF51QE128 Chapter Device OverviewXosc MCU Block DiagramMCF51QE128/64/32 Block Diagram Module Versions V1 ColdFire CoreSystem Clocks Internal Clock Source ICS ModuleSystem Clock Distribution Simplified ICS Block DiagramIcsirclk FLL Engaged External FEE FLL Bypassed Internal Low-Power FbilpICS Modes of Operation FLL Engaged Internal FEIStop Stop FLL Bypassed External Low-Power FbelpGet the latest version from freescale.com Get the latest version from freescale.com Device Pin Assignment Chapter Pins and ConnectionsPin Lqfp Pins in bold are added from the next smaller packageRecommended System Connections Basic System Connections Reset and Rsto PowerOscillator Background / Mode Select BKGD/MS General-Purpose I/O and Peripheral Ports ADC Reference Pins VREFH, VreflNumber Port Pin Alt Pin Assignment by Package and Pin Sharing PriorityPin PriorityPort Pin Alt NumberGet the latest version from freescale.com Chapter Modes of Operation FeaturesIntroduction Overview MCF51QE128/64/32 Power Modes Conceptual DrawingSIM BDC PMC CPU / Power Mode SelectionsRun Stop2 LPrun Mode Regulator StateStop3 Full OnTransition # From Trigger Triggers for Transitions Shown in FigureSecure Mode Debug ModeRun Modes Run ModeLow-Power Run Mode LPrun BDM in Low-Power Run ModeWait Modes Wait ModeLow-Power Wait Mode LPwait BDM in Low-Power Wait ModeStop2 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop Mode Stop3 ModeLow-Range Oscillator Considerations for Stop2 CF1CORE On-Chip Peripheral Modules in Stop and Low-Power ModesLow-Power Mode Behavior Abbreviations used in TableIRQ BDCCOP ICSGet the latest version from freescale.com Get the latest version from freescale.com Kbytes Chapter MemoryMCF51QE128/64/32 Memory Map MCF51QE128Long Byte CPU Access Type Allowed by RegionRegister Addresses and Bit Assignments Read Write Base Address Region ByteColdFire Memory Organization Direct-Page Register Summary Sheet 1 Register Address Name Direct-Page Register Summary Sheet 2Direct-Page Register Summary Sheet 3 High-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 4High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 0x0 0x1 0x2 0x3 Flash Module Reserved Memory LocationsHigh-Page Register Summary Sheet 5 Reserved Flash Memory AddressesNvprot 0x0 0x1 0x2 0x3 0x000004080x0000040C Reserved Flash Memory Addresses RegisterV1 ColdFire Interrupt Controller Memory Map ColdFire Rapid Gpio Memory MapColdFire Interrupt Controller Memory Map V1 ColdFire Rapid Gpio Memory MapIntccfrc RAMFlash IntcsfrcLov-Voltage Programming Sequence Example FeaturesAddresses Desired Value Values Programmed Fcdiv Field Descriptions Register DescriptionsFlash Clock Divider Register Fcdiv Flash Options Register Fopt and Nvopt10. Fopt Field Descriptions Flash Configuration Register Fcnfg13. Flash Protection Address Range Flash Protection Register Fprot and Nvprot11. Fcnfg Field Descriptions 12. Fprot Field Descriptions0x42 0x00-0x3F0x40 0x41 0x00000-0x1EFFFW1c Command buffers are fullFlash Status Register Fstat Fcbef Fccf Fpviol Faccerr Fblank15. Fcmd Field Descriptions Flash Command OperationsFlash Command Register Fcmd Function Description200 195 ÷ 200 = 3% Writing the Fcdiv RegisterALL Program and Erase Command Write SequenceCommands Impossible StartFcmd NVM Flash CommandsErase Verify Command 16. Flash Command DescriptionProgram Command 11. Example Program Command Flow Burst Program Command Programming Sector Erase CommandCommand Buffer Empty Sequential13. Example Sector Erase Command Flow 14. Example Mass Erase Command Flow Mass Erase CommandIllegal Flash Operations Flash Access ViolationsFlash Protection Violations Wait ModeBackground Debug Mode Operating ModesSecurity Unsecuring the MCU using Backdoor Key AccessProgram and Erase Times ResetsFlash Reset Sequence Reset While Flash Command ActiveSecurity Device is unsecure SyncSet PRDIV8 and clock divider fields in CSR3 StopMicrocontroller Reset Chapter Resets, Interrupts, and General System ControlCopclks Copt COP Configuration OptionsComputer Operating Properly COP Watchdog Control Bits Clock Source COP Overflow CountInterrupts and Exceptions Illegal Operation ResetIllegal Address Reset Pin Configuration OptionsExternal Interrupt Initialization Power-On Reset OperationLow-Voltage Detect LVD System Edge and Level SensitivityLow-Voltage Warning LVW Interrupt Operation LVD Reset OperationPeripheral Clock Gating LVD Interrupt OperationIrqpdd Interrupt Pin Request Status and Control Register IrqscIrqsc Register Field Descriptions Irqpdd Irqedg Irqpe Irqf Irqie Irqmod IrqackPOR System Reset Status Register SRSPOR LVR System Options Register 1 SOPT1SOPT1 Register Field Descriptions System Options Register 2 SOPT2IIC1PS SDA1 SCL1 System Device Identification Register SDIDH, SdidlSOPT2 Register Field Descriptions SPI1PS SPSCLK1 MOSI1 MISO1 SS1Sdidl Register Field Descriptions Sdidh Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack LPR Lprs Lpwui Ppde Ppdc Ppdack SPMSC1 Register Field DescriptionsSPMSC2 Register Field Descriptions Lvdvlvwv 11. LVD and LVW Trip Point Typical Values1Lvwf Lvdv Lvwv Lvwie LvwfTPM3 System Clock Gating Control 1 Register SCGC1System Clock Gating Control 2 Register SCGC2 12. SCGC1 Register Field DescriptionsRTC SPI2 SPI1 13. SCGC2 Register Field DescriptionsFLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Port Data and Data Direction Chapter Parallel Input/Output ControlFreescale Semiconductor 113 Data Direction Control Port Data Register Port Read Port Internal Pull-up EnablePort Slew Rate Enable Pull-up, Slew Rate, and Drive StrengthPort Drive Strength Select Port Data Set, Clear and Toggle Data RegistersFreescale Semiconductor 115 Port Data Clear Registers V1 ColdFire Rapid Gpio FunctionalityKeyboard Interrupts Port Data Set RegistersFreescale Semiconductor 117 Edge Only SensitivityEdge and Level Sensitivity Pull-up/Pull-down ResistorsPort a Registers Pin Behavior in Stop ModesParallel I/O, Keyboard Interrupt, and Pin Control Registers Keyboard Interrupt InitializationPTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0 Port a Pull Enable Register PtapePort a Data Register Ptad Port a Data Direction Register PtaddPTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 Port a Slew Rate Enable Register PtasePort a Drive Strength Selection Register Ptads PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0Ptads Register Field Descriptions Port B RegistersPort B Data Register Ptbd Port B Data Direction Register PtbddPtbpe Register Field Descriptions Port B Pull Enable Register PtbpePort B Slew Rate Enable Register Ptbse Ptbdd Register Field Descriptions10. Ptbds Register Field Descriptions Port C RegistersPort B Drive Strength Selection Register Ptbds Port C Data Register Ptcd12. Ptcdd Register Field Descriptions Port C Data Direction Register PtcddPort C Data Set Register Ptcset Port C Data Clear Register Ptcclr16. Ptcpe Register Field Descriptions Port C Pull Enable Register PtcpePort C Toggle Register Ptctog 14. Ptcclr Register Field DescriptionsPort D Data Register Ptdd Port C Slew Rate Enable Register PtcsePort D Registers Port C Drive Strength Selection Register Ptcds20. Ptddd Register Field Descriptions Port D Pull Enable Register PtdpePort D Data Direction Register Ptddd 19. Ptdd Register Field DescriptionsPort E Data Register Pted Port D Slew Rate Enable Register PtdsePort E Registers Port D Drive Strength Selection Register Ptdds25. Ptedd Register Field Descriptions Port E Data Direction Register PteddPort E Data Set Register Pteset 24. Pted Register Field DescriptionsPTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 Port E Pull Enable Register PtepePort E Data Clear Register Pteclr Port E Toggle Register Ptetog30. Ptese Register Field Descriptions Port E Slew Rate Enable Register PtesePort E Drive Strength Selection Register Pteds 29. Ptepe Register Field DescriptionsPort F Data Direction Register Ptfdd Port F Pull Enable Register PtfpePort F Registers Port F Data Register Ptfd35. Ptfse Register Field Descriptions Port F Slew Rate Enable Register PtfsePort F Drive Strength Selection Register Ptfds 34. Ptfpe Register Field Descriptions36. Ptfds Register Field Descriptions Port G RegistersPort G Data Register Ptgd Port G Data Direction Register Ptgdd39. Ptgpe Register Field Descriptions Port G Pull Enable Register PtgpePort G Slew Rate Enable Register Ptgse Port G Drive Strength Selection Register Ptgds41. Ptgds Register Field Descriptions Port H RegistersPort H Data Register Pthd Port H Data Direction Register Pthdd44. Pthpe Register Field Descriptions Port H Pull Enable Register PthpePort H Slew Rate Enable Register Pthse Port H Drive Strength Selection Register PthdsPort J Data Register Ptjd Port J RegistersPort J Data Direction Register Ptjdd 49. Ptjpe Register Field Descriptions Port J Pull Enable Register PtjpePort J Slew Rate Enable Register Ptjse Port J Drive Strength Selection Register Ptjds52. KBI1 Pin Mapping Keyboard Interrupt 1 KBI1 Registers10.1 KBI1 Interrupt Status and Control Register KBI1SC 51. Ptjds Register Field Descriptions10.2 KBI1 Interrupt Pin Select Register KBI1PE Keyboard Interrupt 1 KBI2 Registers10.3 KBI1 Interrupt Edge Select Register KBI1ES 58. KBI2PE Register Field Descriptions 11.1 KBI2 Interrupt Status and Control Register KBI2SC11.2 KBI2 Interrupt Pin Select Register KBI2PE 57. KBI2SC Register Field Descriptions59. KBI2ES Register Field Descriptions 11.3 KBI2 Interrupt Edge Select Register KBI2ESFreescale Semiconductor 143 144 Freescale Semiconductor Overview Chapter ColdFire CoreMemory Map/Register Description ColdFire Core Programming Model Supervisor/User Access RegistersSupervisor Access Only Registers Data Registers D0-D7Supervisor/User Stack Pointers A7 and OTHERA7 Address Registers A0-A6Data Freescale Semiconductor 149 Condition Code Register CCRVector Base Register VBR Program Counter PCCCR Field Descriptions CPU Configuration Register Cpucr SR Field Descriptions Status Register SRBWD Instruction Description Functional DescriptionInstruction Set Architecture Isac Instruction Enhancements over Revision IsaaException Processing Overview Vector Stacked Exception Vector AssignmentsAssignment Numbers Offset Hex Counter SSP → Exception Stack Frame DefinitionAssignment Numbers Offset Hex CounterFS30 Definition Fault Status Encodings2.2 S08 and ColdFire Exception Processing Comparison Format Field EncodingsAttribute S08 V1 ColdFire Exception Processing ComparisonRTI RTE Freescale Semiconductor 159 Access Error ExceptionAddress Error Exception Processor ExceptionsOpwordLine Instruction Class Illegal Instruction Exception10. ColdFire Opword Line Definition Line OpMode Effective AddressTrace Exception Privilege ViolationFreescale Semiconductor 161 Debug Interrupt RTE and Format Error ExceptionUnimplemented Line-A Opcode Unimplemented Line-F OpcodeInterrupt Exception Fault-on-Fault HaltTrap Instruction Exception Unsupported Instruction ExceptionVER REV Reset ExceptionAccess User read-only BDM read-only BDM Load 0x60 D0 Store 0x40 D011. D0 Hardware Configuration Info Field Description Flashsz 12. D1 Hardware Configuration Information Field DescriptionSramsz Address10 Size Bus Additional Operations CR/W Instruction Execution TimingTiming Assumptions 13. Misaligned Operand ReferencesSource Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl Move Instruction Execution Times14. Move Byte and Word Execution Times 15. Move Long Execution Times16. One Operand Instruction Execution Times Standard One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx 17. Two Operand Instruction Execution Times Standard Two Operand Instruction Execution Times18. Miscellaneous Instruction Execution Times Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx 19. General Branch Instruction Execution Times Branch Instruction Execution Times20. Bcc Instruction Execution Times Attribute Chapter Interrupt Controller CF1INTCHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x180 Next 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x1440x148 Next ACMPx 0x14C 0x150 Next SCI2rx 0x154 SCI2tx 0x158To V1 ColdFire core Interrupt Source NumberFreescale Semiconductor 177 Memory Map and Register Definition External Signal DescriptionModes of Operation Intc Force Interrupt Register Intcfrc Memory MapCF1INTC Memory Map Intcfrc Field Descriptions INTCPL6P7,6 Field Descriptions Intc Wake-up Control Register IntcwcrFreescale Semiconductor 181 Intcwcr Field Descriptions Intc Set Interrupt Force Register IntcsfrcENB Offset CF1INTCBASE + 0x1F Intccfrc Intc Clear Interrupt Force Register IntccfrcIntcsfrc Field Descriptions Intccfrc Field DescriptionsVecn Swiack Intc Software and Level-nIACK Registers n = 1,2,3,...,7Priority within Level Midpoint Interrupt Request Level and Priority AssignmentsINTCSWIACK, INTCLVLnIACK Field Descriptions 10. Legend for TableTPM1ch0 TPM1ch1 TPM1ch2 TPM1ovfl 12. V1 ColdFire Interrupt AssignmentsTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Application Information Initialization InformationEmulation of the HCS08’s 1-Level IRQ Handling More on Software IACKs Using INTCPL6P7,6 RegistersFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Freescale Semiconductor 193 Chapter Rapid Gpio RgpioV1 ColdFire Core Freescale Semiconductor 195 RAM Rgpio IFPCore OEP DsocRGPIODATA150 RgpioModule Pin Muxing + Pad Logic On-platform BusRgpio Module External I/O Signals Detailed Signal DescriptionsRgpio Detailed Signal Descriptions Rgpio Write Memory Map Memory Map/Register DefinitionRgpio Read Memory Map DIR Rgpio Data Direction RgpiodirRgpio Data Rgpiodata Rgpiodir Field DescriptionsRgpio Clear Data Rgpioclr Rgpio Pin Enable RgpioenbRgpioset Field Descriptions Rgpio Set Data RgpiosetRgpio Toggle Data Rgpiotog Rgpioclr Field DescriptionsField Description 15-0 Rgpio Toggle Data Application 1 Simple Square-Wave Generation10. Rgpiotog Field Descriptions TOGFrequency @ Relative 11. Square-Wave Output PerformancePeripheral Bus-mapped Gpio Loop29x 12. Emulated SPI Performance using Gpio OutputsSPI Speed @ Relative CPU f = 50 MHz 00x206 Freescale Semiconductor Acmp Clock Gating Acmp Configuration InformationACMP/TPM Configuration Information Chapter Analog Comparator 3V ACMPVLPV1Interrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Stop2 Mode Operation Block DiagramWait Mode Operation Stop3 Mode OperationAcie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF Register DefinitionStatus and Control Register ACMPxSC Acbgs AcpeAcmod InterruptsACMPxSC Field Descriptions Acme214 Freescale Semiconductor ADC Clock Gating Chapter Analog-to-Digital Converter S08ADC12V1Freescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 ADC Channel Assignment Module ConfigurationsChannel Assignments Alternate ClockHardware Trigger Temperature SensorFreescale Semiconductor 219 2provides a block diagram of the ADC moduleName Function Signal PropertiesAD27-AD0 Voltage Reference Low Vrefl Analog Power VddadAnalog Ground Vssad Voltage Reference High VrefhInput Channel Select CocoInput Select Adact Status and Control Register 2 ADCSC2Data Result High Register Adcrh ADCSC2 Register Field DescriptionsADCV11 ADCV10 ADCV9 ADCV8 Data Result Low Register AdcrlCompare Value High Register Adccvh ADR10 ADR9 ADR8Adlpc Configuration Register AdccfgCompare Value Low Register Adccvl Adccfg Register Field DescriptionsInput Clock Select Pin Control 1 Register APCTL1Clock Divide Select Conversion Modes10. APCTL1 Register Field Descriptions Pin Control 2 Register APCTL2ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 ADPC23 Pin Control 3 Register APCTL311. APCTL2 Register Field Descriptions ADPC15ADPC16 12. APCTL3 Register Field DescriptionsADPC21 ADPC20Conversion Control Clock Select and Divide ControlInput Select and Pin Control Hardware TriggerFreescale Semiconductor 231 Initiating ConversionsCompleting Conversions Aborting ConversionsAdiclk Adlsmp Power ControlSample Time and Total Conversion Time 13. Total Conversion Time vs. Control ConditionsAutomatic Compare Function MCU Wait Mode OperationStop3 Mode With Adack Enabled MCU Stop3 Mode OperationMCU Stop2 Mode Operation Stop3 Mode With Adack DisabledFreescale Semiconductor 235 ADC Module Initialization ExampleInitialization Sequence Pseudo-Code ExampleYes Read Adcrh Then Adcrl To Clear Coco Bit Continue External Pins and RoutingReset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No COCO=1?Freescale Semiconductor 237 Analog Supply PinsAnalog Reference Pins Analog Input PinsNoise-Induced Errors Sources of ErrorSampling Error Pin Leakage ErrorFreescale Semiconductor 239 Code Width and Quantization ErrorLinearity Errors Lsb =Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor Freescale Semiconductor 243 Stop2 Mode ConsiderationsChapter Internal Clock Source S08ICSV3 External OscillatorInternal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor Freescale Semiconductor 247 HGO, RANGE, EREFS, ERCLKEN, Erefsten2is the ICS block diagram Rdiv Irefs FLL Bypassed Internal Low Power FbilpFLL Bypassed External Low Power Fbelp ICS Register SummaryReference Divide Factor ICS Control Register 1 ICSC1ICSC1 Field Descriptions Clks Rdiv Irefs Irclken IrefstenBdiv Range HGO Erefs Erclken Erefsten ICS Control Register 2 ICSC2ICS Trim Register Icstrm ICSC2 Field DescriptionsDMX32 Irefst Clkst Oscinit FTRIM1 DRS ICS Status and Control IcsscIcstrm Field Descriptions Icssc Field Descriptions1024 32 40 MHz Reference range FLL factor DCO range512 16 20 MHz 608 19.92 MHzIREFS=0 CLKS=10 Operational ModesFLL Engaged Internal FEI IREFS=1 CLKS=00 IREFS=0FLL Bypassed External FBE FLL Bypassed Internal Low Power FbilpFLL Engaged External FEE FLL Bypassed Internal FBIStop Mode SwitchingFLL Bypassed External Low Power Fbelp Bus Frequency DividerExternal Reference Clock Low Power Bit UsageDCO Maximum Frequency with 32.768 kHz Oscillator Internal Reference ClockLocal Clock Fixed Frequency ClockSOPT2IIC1PS Module ConfigurationChapter Inter-Integrated Circuit S08IICV2 IIC1 Position OptionsMCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SDA Serial Data Line SCL Serial Clock LineFreescale Semiconductor 263 = Unimplemented or Reserved IIC Address Register IicaIIC Frequency Divider Register Iicf Iica Field DescriptionsMult ICR SDA Iicf Field DescriptionsHold Time Values for 8 MHz Bus Speed Hold Times μsICR SCL IIC Divider and Hold ValuesIICC1 Field Descriptions IIC Control Register IICC1Iics Field Descriptions IIC Status Register IicsTCF Freescale Semiconductor 269 IIC Data I/O Register IicdIIC Control Register 2 IICC2 Iicd Field DescriptionsIICC2 Field Descriptions IIC ProtocolGcaen Slave Address Transmission Start SignalFreescale Semiconductor 271 Data Transfer Stop SignalRepeated Start Signal Arbitration ProcedureFreescale Semiconductor 273 Clock SynchronizationHandshaking Clock StretchingMaster-Transmitter Addresses a Slave-Receiver 13.4.2 10-bit AddressMaster-Receiver Addresses a Slave-Transmitter Address Detect Interrupt ResetsGeneral Call Address Byte Transfer Interrupt276 Freescale Semiconductor Module Use Initialization/Application InformationModule Initialization Slave Module Initialization Master12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor RTC Modes of Operation Chapter Real-Time Counter S08RTCV1ADC Hardware Trigger RTC Clock SourcesInterrupt Vector Freescale Semiconductor 283 MCF51QE128 Block Diagram Highlighting RTC Block and PinsActive Background Mode Irclk RTC Register SummaryLPO ErclkRtif RTC Status and Control Register RtcscRtcsc Field Descriptions RTC Prescaler Divide-by valuesRtcmod Field Descriptions RTC Counter Register RtccntRTC Modulo Register Rtcmod Rtccnt Field DescriptionsKHz Internal Clock MHz External Clock Rtclks = RTC Operation ExamplePrescaler Period RtcpsFreescale Semiconductor 289 Internal 1-kHz Clock Source RTC Clock Rtcps =Rtccnt Rtif 0x52 0x53 0x54 0x55 0x00 0x01290 Freescale Semiconductor SCI Clock Gating Chapter Serial Communications Interface S08SCIV4Freescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 × Baud Rate Clock SCI Transmitter Block DiagramFreescale Semiconductor 297 SCI Receiver Block DiagramSCIxBDH Field Descriptions SCI Baud Rate Registers SCIxBDH, SCIxBDLLbkdie Loops SCI Control Register 1 SCIxC1SCIxBDL Field Descriptions Loops Sciswai Rsrc Wake ILTSCIxC2 Field Descriptions SCI Control Register 2 SCIxC2TIE Tdre Rdrf Idle SCI Status Register 1 SCIxS1SCIxD Framing errorNo parity error Parity errorRXINV1 SCI Status Register 2 SCIxS2SCIxS2 Field Descriptions Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAFTXINV1 SCI Control Register 3 SCIxC3SCIxC3 Field Descriptions TxdirBaud Rate Generation SCI Data Register SCIxDFreescale Semiconductor 305 Send Break and Queued Idle Transmitter Functional DescriptionBRK13 Receiver Functional DescriptionData Sampling Technique Break Character LengthIdle-Line Wakeup Receiver Wakeup OperationFreescale Semiconductor 309 Interrupts and Status Flags15.3.5.1 8- and 9-Bit Data Modes Stop Mode OperationLoop Mode Additional SCI FunctionsFreescale Semiconductor 311 Single-Wire Operation312 Freescale Semiconductor SPI Clock Gating Chapter Serial Peripheral Interface S08SPIV3Freescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor SPI System Block Diagram Block DiagramsFreescale Semiconductor 317 SPI Module Block Diagram Freescale Semiconductor 319 SPI Baud Rate GenerationSS Slave Select Spsck SPI Serial ClockMosi Master Data Out, Slave Data Miso Master Data In, Slave Data OutSPIxC1 Field Descriptions Modes of OperationSPI in Stop Modes SPI Control Register 1 SPIxC1Modfen Ssoe Master Mode Slave ModeSPI Control Register 2 SPIxC2 SS Pin FunctionModfen Bidiroe Spiswai SPI Stop in Wait ModeSPI Baud Rate Register SPIxBR SPIxC2 Register Field DescriptionsSPR SPI Status Register SPIxSSPIxBR Register Field Descriptions SpprSPI Data Register SPIxD SPI Clock Formats Freescale Semiconductor 327 10. SPI Clock Formats Cpha =11. SPI Clock Formats Cpha = SPI InterruptsFreescale Semiconductor 329 Mode Fault Detection330 Freescale Semiconductor TPM Clock Gating Chapter Timer/Pulse-Width Modulator S08TPMV3Freescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor Freescale Semiconductor 337 TPM Block DiagramExtclk Signal DescriptionExtclk External Clock Source TPMxCHn TPM Channel n I/O PinsFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TOF TPM Status and Control Register TPMxSCTPMxSC Field Descriptions TOF Toie Cpwms Clksb Clksa PS2 PS1Clksbclksa TPM Counter Registers TPMxCNTHTPMxCNTLTPM-Clock-Source Selection Prescale Factor SelectionFreescale Semiconductor 343 TPM Counter Modulo Registers TPMxMODHTPMxMODLTPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter TPMxCNT70 Any write to TPMxCNTL clears the 16-bit counterCHnF CHnIE MSnB MSnA ELSnB ELSnA TPM Channel n Status and Control Register TPMxCnSCTPMxMOD158 TPMxMOD70Cpwms MSnBMSnA ELSnBELSnA Mode ConfigurationTPMxCnSC Field Descriptions Mode, Edge, and Level SelectionTPMxCnV70 TPM Channel Value Registers TPMxCnVHTPMxCnVLMode, Edge, and Level Selection TPMxCnV158Counter Clock Source CounterFreescale Semiconductor 347 TPM Clock Source Selection Counter Overflow and Modulo ResetOutput Compare Mode Channel Mode SelectionManual Counter Reset Input Capture Mode15. PWM Period and Pulse Width ELSnA=0 Edge-Aligned PWM ModeFreescale Semiconductor 351 Center-Aligned PWM ModeDescription of Reset Operation Reset OverviewGeneral Interrupt Summary Timer Overflow Interrupt TOF DescriptionInterrupt Local Source Description Enable Description of Interrupt OperationCenter-Aligned PWM Case Channel Event Interrupt DescriptionFreescale Semiconductor 355 Chapter Version 1 ColdFire Debug CF1DEBUGBkgd BDC Version 1 ColdFire Core CF1CoreOEP PSTCsrhrl CSR2D1HRL Modes of OperationsDebug Revision Summary RevisionBDM? BDM Command TypesCommand Type Flash Core Status Command SetENBDM=1 External Signal DescriptionsDebug Module Signals Description BDM GODebug Module Memory Map DRc Register Name Width Access Reset Value Section BitsCPU Configuration/Status Register CSR Bstat FOF TRG Halt Bkpt HRL BKD IPW CSR Field DescriptionsTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Xcsr Reference Summary Extended Configuration/Status Register XcsrMethod Reference Details CPU State CPU Cstat Halt Stop Eseqc Clksw SEC Erase EnbdmApcsc Apce XcsrSEC R Eseqc WErase W Syncpc Interval Configuration/Status Register 2 CSR2CSR2 Reference Summary Xcsr CSR2CSR2 Field Descriptions Pstb Valid Data Locations Oldest to Newest PSTBWA7Start Condition Stop Condition Configuration/Status Register 3 CSR310. CSR3 Reference Summary PstbssBFC Bfcdiv DIV8 BDM Address Attribute Register BaarBFCDIV8 SZM TTM TMM Address Attribute Trigger Register AatrSZM Signal of the processor’s local busBDM memory commands Normal processor access Else Reserved Trigger Definition Register TDRL1EA L2EDL2EA L2T L1TL2T Program Counter Breakpoint/Mask Registers PBR0-3, Pbmr Three bits disables the address breakpointNo inversion Invert data breakpoint comparators DRc 0x09 Pbmr Mask Reset15. PBR0 Field Descriptions DRc 0x08 PBR0Ablr Address Breakpoint Registers ABLR, Abhr17. Pbmr Field Descriptions Abhr19. Abhr Field Description Data Breakpoint and Mask Registers DBR, Dbmr21. Dbmr Field Descriptions Resulting Set of Possible Trigger Combinations Background Debug Mode BDM22. Access Size and Operand Data Location Address1 Access Size Operand LocationCpucrard = CPU Halt23. CPU Halt Sources Halt Source Halt Timing DescriptionCpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details Freescale Semiconductor 385 15. BDC Host-to-Target Serial Bit Timing16. BDC Target-to-Host Serial Bit Timing Logic Freescale Semiconductor 387 BDM Command Set DescriptionsPST Trace Buffer Read Commands Miscellaneous CommandsMemory Commands Core Register CommandsVBR 24. BDM Command Code Field DescriptionsCRG CRG CRNAckenable BDM Command Set Summary25. BDM Command Summary AckdisableReaddreg ReadcregReadpstb Writecreg SyncpcFreescale Semiconductor 393 Disable host/target handshake protocol Always AvailableEnable host/target handshake protocol Always Available 0x03Enter active background mode if enabled Non-intrusive Xcsrsb 0x12 Memory 0x12 Memory data7-0Target 0x16 Memory Data15-8 Memory data7-0 TargetRead CPU control register Active Background No operation Non-intrusiveTarget Memory data7-0 Target → Host Read debug control register Non-intrusive0xA0+CRN Host → Target Dreg data 0x30 Address23-00x50+CRN Host → Target Pstb data 0x310x35 0x39Read CSR3 Status Byte Always Available Read general-purpose CPU register Active BackgroundRead Xcsr Status Byte Always Available Read CSR2 Status Byte Always AvailableFreescale Semiconductor 401 Synchronize PC to PST/DDATA Signals Non-intrusiveWrite CPU control register Active Background 0xC0+CRN Creg dataHost → target Write debug control register Non-intrusive0x80+CRN Dreg data 0x10 Address23-0 Memory Data7-0Write general-purpose CPU register Active Background Write CSR3 Status Byte Always Available Serial Interface Hardware Handshake ProtocolWrite Xcsr Status Byte Always Available Write CSR2 Status Byte Always AvailableFreescale Semiconductor 405 19. Target Acknowledge Pulse ACK20. Handshake Protocol at Command Level Hardware Handshake Abort ProcedureFreescale Semiconductor 407 21signal timing is not drawn to scale21. ACK Abort Procedure at the Command Level Real-Time Trace Support Real-Time Debug SupportFreescale Semiconductor 409 Instructions, generate different encodings Enter user mode26. Processor Status Encodings PST40 Definition0x08-0x0B Begin Execution of Taken Branch PST =Freescale Semiconductor 411 PST Values Description 23. Example JMP Instruction Output in PstbPstbddata PST Trace Buffer Pstb18.4.3.3 PST/DDATA Example PstbpstProcessor Status, Debug Data Definition Freescale Semiconductor 415 27. PST/DDATA Specification for User-Mode InstructionsInstruction Operand Syntax PST/DDATA416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set Freescale Semiconductor 419 GND ResetFreescale-Recommended BDM Pinout No Connect420 Freescale Semiconductor Chapter Description Appendix a Revision HistoryChanges between Rev and Rev MCF51QE128RM Rev to Rev ChangesRevision History Page How to Reach Us