Freescale Semiconductor MCF51QE128RM Read debug control register Non-intrusive, 0x30 Address23-0

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

If the processor is halted, this command reads the selected control register and returns the 32-bit result. This register grouping includes the PC, SR, CPUCR, VBR, and OTHER_A7. Accesses to processor control registers are always 32-bits wide, regardless of implemented register width. The register is addressed through the core register number (CRN). See Table 18-24for the CRN details when CRG is 11.

If the processor is not halted, this command is rejected as an illegal operation and no operation is performed.

18.4.1.5.10 READ_DREG

Read debug control register Non-intrusive

0xA0+CRN

host →

target

	DREG data	DREG data	DREG data	DREG data
	[31-24]	[23-16]	[15-8]	[7-0]
D	target →	target →	target →	target →
L	host	host	host	host
Y

This command reads the selected debug control register and returns the 32-bit result. This register grouping includes the CSR, XCSR, CSR2, and CSR3. Accesses to debug control registers are always

32-bits wide, regardless of implemented register width. The register is addressed through the core register number (CRN). See Table 18-4for CRN details.

18.4.1.5.11 READ_MEM.sz, READ_MEM.sz_WS

READ_MEM.sz

Read memory at the specified address Non-intrusive

0x30	Address[23-0]
host →	host →
target	target

Memory data[7-0]

Dtarget →

L

Y host

0x34	Address[23-0]		Memory	Memory
			data[15-8]	data[7-0]
host →	host →	D	target →	target →
target	target	L	host	host
		Y
0x38	Address[23-0]		Memory	Memory	Memory		Memory
			data[31-24]	data[23-16]	data[15-8]		data[7-0]
host →	host →	D	target →	target →	target →		target →
target	target	L	host	host		host	host
		Y

MCF51QE128 MCU Series Reference Manual, Rev. 3

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