MCF51QE64 MCF51QE32
Page
MCF51QE128 Series Features
Page
MCF51QE128 Reference Manual
MCF51QE128 MCU Series Reference Manual, Rev
Contents
Section Number Title
Chapter Resets, Interrupts, and General System Control
Freescale Semiconductor
Title Chapter Parallel Input/Output Control
127
ColdFire Core
Chapter Interrupt Controller CF1INTC
Analog Comparator 3V ACMPVLPV1
11.1.5
Internal Clock Source S08ICSV3
Section Number Title
Chapter Inter-Integrated Circuit S08IICV2
Real-Time Counter S08RTCV1
Serial Peripheral Interface S08SPIV3
Chapter Timer/Pulse-Width Modulator S08TPMV3
Chapter Version 1 ColdFire Debug CF1DEBUG
Appendix a Revision History
Chapter Device Overview
MCF51QE128 Series Features by MCU and Package
Feature MCF51QE128
Devices in the MCF51QE128/64/32 Series
MCU Block Diagram
Xosc
MCF51QE128/64/32 Block Diagram
Internal Clock Source ICS Module
V1 ColdFire Core
System Clocks
Module Versions
Simplified ICS Block Diagram
System Clock Distribution
Icsirclk
FLL Engaged Internal FEI
FLL Bypassed Internal Low-Power Fbilp
ICS Modes of Operation
FLL Engaged External FEE
FLL Bypassed External Low-Power Fbelp
Stop Stop
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Chapter Pins and Connections
Device Pin Assignment
Pins in bold are added from the next smaller package
Pin Lqfp
Recommended System Connections
Basic System Connections
Power
Reset and Rsto
Oscillator
Background / Mode Select BKGD/MS
ADC Reference Pins VREFH, Vrefl
General-Purpose I/O and Peripheral Ports
Priority
Pin Assignment by Package and Pin Sharing Priority
Pin
Number Port Pin Alt
Number
Port Pin Alt
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Features
Chapter Modes of Operation
Introduction
MCF51QE128/64/32 Power Modes Conceptual Drawing
Overview
CPU / Power Mode Selections
PMC
Full On
Mode Regulator State
Stop3
Run Stop2 LPrun
Triggers for Transitions Shown in Figure
Transition # From Trigger
Debug Mode
Secure Mode
BDM in Low-Power Run Mode
Run Mode
Low-Power Run Mode LPrun
Run Modes
BDM in Low-Power Wait Mode
Wait Mode
Low-Power Wait Mode LPwait
Wait Modes
Stop2 Mode
Stop3 Mode
Stop4 Low Voltage Detect or BDM Enabled in Stop Mode
Low-Range Oscillator Considerations for Stop2
Abbreviations used in Table
On-Chip Peripheral Modules in Stop and Low-Power Modes
Low-Power Mode Behavior
CF1CORE
ICS
BDC
COP
IRQ
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Kbytes
Chapter Memory
MCF51QE128/64/32 Memory Map
RAM
Read Write Base Address Region Byte
CPU Access Type Allowed by Region
Register Addresses and Bit Assignments
Long Byte
ColdFire Memory Organization
Direct-Page Register Summary Sheet 1
Direct-Page Register Summary Sheet 2
Register Address Name
Direct-Page Register Summary Sheet 3
Direct-Page Register Summary Sheet 4
High-Page Register Summary Sheet 1
High-Page Register Summary Sheet 2
High-Page Register Summary Sheet 3
High-Page Register Summary Sheet 4
Reserved Flash Memory Addresses
Flash Module Reserved Memory Locations
High-Page Register Summary Sheet 5
0x0 0x1 0x2 0x3
Reserved Flash Memory Addresses Register
0x0 0x1 0x2 0x3 0x00000408
0x0000040C
Nvprot
V1 ColdFire Rapid Gpio Memory Map
ColdFire Rapid Gpio Memory Map
ColdFire Interrupt Controller Memory Map
V1 ColdFire Interrupt Controller Memory Map
Intcsfrc
RAM
Flash
Intccfrc
Features
Lov-Voltage Programming Sequence Example
Addresses Desired Value Values Programmed
Flash Options Register Fopt and Nvopt
Register Descriptions
Flash Clock Divider Register Fcdiv
Fcdiv Field Descriptions
Flash Configuration Register Fcnfg
10. Fopt Field Descriptions
12. Fprot Field Descriptions
Flash Protection Register Fprot and Nvprot
11. Fcnfg Field Descriptions
13. Flash Protection Address Range
0x41 0x00000-0x1EFFF
0x00-0x3F
0x40
0x42
Fcbef Fccf Fpviol Faccerr Fblank
Command buffers are full
Flash Status Register Fstat
W1c
Function Description
Flash Command Operations
Flash Command Register Fcmd
15. Fcmd Field Descriptions
Writing the Fcdiv Register
200 195 ⎟ 200 = 3%
Start
Command Write Sequence
Commands Impossible
ALL Program and Erase
16. Flash Command Description
Flash Commands
Erase Verify Command
Fcmd NVM
Program Command
11. Example Program Command Flow
Burst Program Command
Sequential
Sector Erase Command
Command Buffer Empty
Programming
13. Example Sector Erase Command Flow
Mass Erase Command
14. Example Mass Erase Command Flow
Flash Access Violations
Illegal Flash Operations
Operating Modes
Wait Mode
Background Debug Mode
Flash Protection Violations
Unsecuring the MCU using Backdoor Key Access
Security
Reset While Flash Command Active
Resets
Flash Reset Sequence
Program and Erase Times
Security
Stop
Sync
Set PRDIV8 and clock divider fields in CSR3
Device is unsecure
Chapter Resets, Interrupts, and General System Control
Microcontroller Reset
Control Bits Clock Source COP Overflow Count
COP Configuration Options
Computer Operating Properly COP Watchdog
Copclks Copt
Pin Configuration Options
Illegal Operation Reset
Illegal Address Reset
Interrupts and Exceptions
Edge and Level Sensitivity
Power-On Reset Operation
Low-Voltage Detect LVD System
External Interrupt Initialization
LVD Interrupt Operation
LVD Reset Operation
Peripheral Clock Gating
Low-Voltage Warning LVW Interrupt Operation
Irqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack
Interrupt Pin Request Status and Control Register Irqsc
Irqsc Register Field Descriptions
Irqpdd
System Reset Status Register SRS
POR
System Options Register 1 SOPT1
POR LVR
System Options Register 2 SOPT2
SOPT1 Register Field Descriptions
SPI1PS SPSCLK1 MOSI1 MISO1 SS1
System Device Identification Register SDIDH, Sdidl
SOPT2 Register Field Descriptions
IIC1PS SDA1 SCL1
Sdidh Register Field Descriptions
Sdidl Register Field Descriptions
Lvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack
SPMSC1 Register Field Descriptions
LPR Lprs Lpwui Ppde Ppdc Ppdack
SPMSC2 Register Field Descriptions
Lvwf
11. LVD and LVW Trip Point Typical Values1
Lvwf Lvdv Lvwv Lvwie
Lvdvlvwv
12. SCGC1 Register Field Descriptions
System Clock Gating Control 1 Register SCGC1
System Clock Gating Control 2 Register SCGC2
TPM3
13. SCGC2 Register Field Descriptions
RTC SPI2 SPI1
FLS
Freescale Semiconductor 109
110 Freescale Semiconductor
Freescale Semiconductor 111
112 Freescale Semiconductor
Chapter Parallel Input/Output Control
Port Data and Data Direction
Freescale Semiconductor 113
Pull-up, Slew Rate, and Drive Strength
Port Internal Pull-up Enable
Port Slew Rate Enable
Data Direction Control Port Data Register Port Read
Port Data Set, Clear and Toggle Data Registers
Port Drive Strength Select
Freescale Semiconductor 115
Port Data Set Registers
V1 ColdFire Rapid Gpio Functionality
Keyboard Interrupts
Port Data Clear Registers
Pull-up/Pull-down Resistors
Edge Only Sensitivity
Edge and Level Sensitivity
Freescale Semiconductor 117
Keyboard Interrupt Initialization
Pin Behavior in Stop Modes
Parallel I/O, Keyboard Interrupt, and Pin Control Registers
Port a Registers
Port a Data Direction Register Ptadd
Port a Pull Enable Register Ptape
Port a Data Register Ptad
PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
Port a Slew Rate Enable Register Ptase
Port a Drive Strength Selection Register Ptads
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
Port B Data Direction Register Ptbdd
Port B Registers
Port B Data Register Ptbd
Ptads Register Field Descriptions
Ptbdd Register Field Descriptions
Port B Pull Enable Register Ptbpe
Port B Slew Rate Enable Register Ptbse
Ptbpe Register Field Descriptions
Port C Data Register Ptcd
Port C Registers
Port B Drive Strength Selection Register Ptbds
10. Ptbds Register Field Descriptions
Port C Data Clear Register Ptcclr
Port C Data Direction Register Ptcdd
Port C Data Set Register Ptcset
12. Ptcdd Register Field Descriptions
14. Ptcclr Register Field Descriptions
Port C Pull Enable Register Ptcpe
Port C Toggle Register Ptctog
16. Ptcpe Register Field Descriptions
Port C Drive Strength Selection Register Ptcds
Port C Slew Rate Enable Register Ptcse
Port D Registers
Port D Data Register Ptdd
19. Ptdd Register Field Descriptions
Port D Pull Enable Register Ptdpe
Port D Data Direction Register Ptddd
20. Ptddd Register Field Descriptions
Port D Drive Strength Selection Register Ptdds
Port D Slew Rate Enable Register Ptdse
Port E Registers
Port E Data Register Pted
24. Pted Register Field Descriptions
Port E Data Direction Register Ptedd
Port E Data Set Register Pteset
25. Ptedd Register Field Descriptions
Port E Toggle Register Ptetog
Port E Pull Enable Register Ptepe
Port E Data Clear Register Pteclr
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
29. Ptepe Register Field Descriptions
Port E Slew Rate Enable Register Ptese
Port E Drive Strength Selection Register Pteds
30. Ptese Register Field Descriptions
Port F Data Register Ptfd
Port F Pull Enable Register Ptfpe
Port F Registers
Port F Data Direction Register Ptfdd
34. Ptfpe Register Field Descriptions
Port F Slew Rate Enable Register Ptfse
Port F Drive Strength Selection Register Ptfds
35. Ptfse Register Field Descriptions
Port G Data Direction Register Ptgdd
Port G Registers
Port G Data Register Ptgd
36. Ptfds Register Field Descriptions
Port G Drive Strength Selection Register Ptgds
Port G Pull Enable Register Ptgpe
Port G Slew Rate Enable Register Ptgse
39. Ptgpe Register Field Descriptions
Port H Data Direction Register Pthdd
Port H Registers
Port H Data Register Pthd
41. Ptgds Register Field Descriptions
Port H Drive Strength Selection Register Pthds
Port H Pull Enable Register Pthpe
Port H Slew Rate Enable Register Pthse
44. Pthpe Register Field Descriptions
Port J Registers
Port J Data Register Ptjd
Port J Data Direction Register Ptjdd
Port J Drive Strength Selection Register Ptjds
Port J Pull Enable Register Ptjpe
Port J Slew Rate Enable Register Ptjse
49. Ptjpe Register Field Descriptions
51. Ptjds Register Field Descriptions
Keyboard Interrupt 1 KBI1 Registers
10.1 KBI1 Interrupt Status and Control Register KBI1SC
52. KBI1 Pin Mapping
Keyboard Interrupt 1 KBI2 Registers
10.2 KBI1 Interrupt Pin Select Register KBI1PE
10.3 KBI1 Interrupt Edge Select Register KBI1ES
57. KBI2SC Register Field Descriptions
11.1 KBI2 Interrupt Status and Control Register KBI2SC
11.2 KBI2 Interrupt Pin Select Register KBI2PE
58. KBI2PE Register Field Descriptions
11.3 KBI2 Interrupt Edge Select Register KBI2ES
59. KBI2ES Register Field Descriptions
Freescale Semiconductor 143
144 Freescale Semiconductor
Chapter ColdFire Core
Overview
Memory Map/Register Description
Data Registers D0-D7
Supervisor/User Access Registers
Supervisor Access Only Registers
ColdFire Core Programming Model
Address Registers A0-A6
Supervisor/User Stack Pointers A7 and OTHERA7
Data
Condition Code Register CCR
Freescale Semiconductor 149
Program Counter PC
Vector Base Register VBR
CCR Field Descriptions
CPU Configuration Register Cpucr
Status Register SR
SR Field Descriptions
BWD
Instruction Enhancements over Revision Isaa
Functional Description
Instruction Set Architecture Isac
Instruction Description
Exception Processing Overview
Exception Vector Assignments
Vector Stacked
Assignment Numbers Offset Hex Counter
Numbers Offset Hex Counter
Exception Stack Frame Definition
Assignment
SSP →
Format Field Encodings
Fault Status Encodings
2.2 S08 and ColdFire Exception Processing Comparison
FS30 Definition
Exception Processing Comparison
Attribute S08 V1 ColdFire
RTI RTE
Processor Exceptions
Access Error Exception
Address Error Exception
Freescale Semiconductor 159
Line OpMode Effective Address
Illegal Instruction Exception
10. ColdFire Opword Line Definition
OpwordLine Instruction Class
Privilege Violation
Trace Exception
Freescale Semiconductor 161
Unimplemented Line-F Opcode
RTE and Format Error Exception
Unimplemented Line-A Opcode
Debug Interrupt
Unsupported Instruction Exception
Fault-on-Fault Halt
Trap Instruction Exception
Interrupt Exception
BDM Load 0x60 D0 Store 0x40 D0
Reset Exception
Access User read-only BDM read-only
VER REV
11. D0 Hardware Configuration Info Field Description
12. D1 Hardware Configuration Information Field Description
Flashsz
Sramsz
13. Misaligned Operand References
Instruction Execution Timing
Timing Assumptions
Address10 Size Bus Additional Operations CR/W
15. Move Long Execution Times
Move Instruction Execution Times
14. Move Byte and Word Execution Times
Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl
Standard One Operand Instruction Execution Times
16. One Operand Instruction Execution Times
Effective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx
Standard Two Operand Instruction Execution Times
17. Two Operand Instruction Execution Times
Miscellaneous Instruction Execution Times
18. Miscellaneous Instruction Execution Times
Opcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx
Branch Instruction Execution Times
19. General Branch Instruction Execution Times
20. Bcc Instruction Execution Times
Chapter Interrupt Controller CF1INTC
Attribute
HCS08
Interrupt Controller CF1INTC
V1 ColdFire Exception Vector Table
0x150 Next SCI2rx 0x154 SCI2tx 0x158
0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x144
0x148 Next ACMPx 0x14C
0x180 Next
Interrupt Source Number
To V1 ColdFire core
Freescale Semiconductor 177
External Signal Description
Memory Map and Register Definition
Modes of Operation
Memory Map
Intc Force Interrupt Register Intcfrc
CF1INTC Memory Map
Intcfrc Field Descriptions
Intc Wake-up Control Register Intcwcr
INTCPL6P7,6 Field Descriptions
Freescale Semiconductor 181
Intc Set Interrupt Force Register Intcsfrc
Intcwcr Field Descriptions
ENB
Intccfrc Field Descriptions
Intc Clear Interrupt Force Register Intccfrc
Intcsfrc Field Descriptions
Offset CF1INTCBASE + 0x1F Intccfrc
Intc Software and Level-nIACK Registers n = 1,2,3,...,7
Vecn Swiack
10. Legend for Table
Interrupt Request Level and Priority Assignments
INTCSWIACK, INTCLVLnIACK Field Descriptions
Priority within Level Midpoint
12. V1 ColdFire Interrupt Assignments
TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovfl
TPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl
Handling of Non-Maskable Level 7 Interrupt Requests
Initialization Information
Application Information
Emulation of the HCS08’s 1-Level IRQ Handling
Using INTCPL6P7,6 Registers
More on Software IACKs
Freescale Semiconductor 189
ISR Code Snippet with Swiack
Freescale Semiconductor 191
192 Freescale Semiconductor
Chapter Rapid Gpio Rgpio
Freescale Semiconductor 193
V1 ColdFire Core
Freescale Semiconductor 195
OEP Dsoc
IFP
Core
RAM Rgpio
Pin Muxing + Pad Logic On-platform Bus
Rgpio
Module
RGPIODATA150
Detailed Signal Descriptions
Rgpio Module External I/O Signals
Rgpio Detailed Signal Descriptions
Memory Map/Register Definition
Rgpio Write Memory Map
Rgpio Read Memory Map
Rgpiodir Field Descriptions
Rgpio Data Direction Rgpiodir
Rgpio Data Rgpiodata
DIR
Rgpio Pin Enable Rgpioenb
Rgpio Clear Data Rgpioclr
Rgpioclr Field Descriptions
Rgpio Set Data Rgpioset
Rgpio Toggle Data Rgpiotog
Rgpioset Field Descriptions
TOG
Application 1 Simple Square-Wave Generation
10. Rgpiotog Field Descriptions
Field Description 15-0 Rgpio Toggle Data
11. Square-Wave Output Performance
29x
12. Emulated SPI Performance using Gpio Outputs
SPI Speed @ Relative CPU f = 50 MHz
Freescale Semiconductor 205
206 Freescale Semiconductor
Chapter Analog Comparator 3V ACMPVLPV1
Acmp Configuration Information
ACMP/TPM Configuration Information
Acmp Clock Gating
Interrupt Vectors
Freescale Semiconductor 209
210 Freescale Semiconductor
Stop3 Mode Operation
Block Diagram
Wait Mode Operation
Stop2 Mode Operation
Acbgs Acpe
Register Definition
Status and Control Register ACMPxSC
Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF
Acme
Interrupts
ACMPxSC Field Descriptions
Acmod
214 Freescale Semiconductor
Chapter Analog-to-Digital Converter S08ADC12V1
ADC Clock Gating
Freescale Semiconductor 215
Analog-to-Digital Converter S08ADC12V1
Alternate Clock
Module Configurations
Channel Assignments
ADC Channel Assignment
Temperature Sensor
Hardware Trigger
2provides a block diagram of the ADC module
Freescale Semiconductor 219
Signal Properties
Name Function
AD27-AD0
Voltage Reference High Vrefh
Analog Power Vddad
Analog Ground Vssad
Voltage Reference Low Vrefl
Coco
Input Channel Select
Input Select
ADCSC2 Register Field Descriptions
Status and Control Register 2 ADCSC2
Data Result High Register Adcrh
Adact
ADR10 ADR9 ADR8
Data Result Low Register Adcrl
Compare Value High Register Adccvh
ADCV11 ADCV10 ADCV9 ADCV8
Adccfg Register Field Descriptions
Configuration Register Adccfg
Compare Value Low Register Adccvl
Adlpc
Conversion Modes
Pin Control 1 Register APCTL1
Clock Divide Select
Input Clock Select
Pin Control 2 Register APCTL2
10. APCTL1 Register Field Descriptions
ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
ADPC15
Pin Control 3 Register APCTL3
11. APCTL2 Register Field Descriptions
ADPC23
ADPC20
12. APCTL3 Register Field Descriptions
ADPC21
ADPC16
Hardware Trigger
Clock Select and Divide Control
Input Select and Pin Control
Conversion Control
Aborting Conversions
Initiating Conversions
Completing Conversions
Freescale Semiconductor 231
13. Total Conversion Time vs. Control Conditions
Power Control
Sample Time and Total Conversion Time
Adiclk Adlsmp
MCU Wait Mode Operation
Automatic Compare Function
Stop3 Mode With Adack Disabled
MCU Stop3 Mode Operation
MCU Stop2 Mode Operation
Stop3 Mode With Adack Enabled
Pseudo-Code Example
ADC Module Initialization Example
Initialization Sequence
Freescale Semiconductor 235
COCO=1?
External Pins and Routing
Reset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No
Yes Read Adcrh Then Adcrl To Clear Coco Bit Continue
Analog Input Pins
Analog Supply Pins
Analog Reference Pins
Freescale Semiconductor 237
Pin Leakage Error
Sources of Error
Sampling Error
Noise-Induced Errors
Lsb =
Code Width and Quantization Error
Linearity Errors
Freescale Semiconductor 239
Code Jitter, Non-Monotonicity, and Missing Codes
Freescale Semiconductor 241
242 Freescale Semiconductor
External Oscillator
Stop2 Mode Considerations
Chapter Internal Clock Source S08ICSV3
Freescale Semiconductor 243
Internal Clock Source S08ICSV3
Freescale Semiconductor 245
246 Freescale Semiconductor
HGO, RANGE, EREFS, ERCLKEN, Erefsten
Freescale Semiconductor 247
2is the ICS block diagram
ICS Register Summary
FLL Bypassed Internal Low Power Fbilp
FLL Bypassed External Low Power Fbelp
Rdiv Irefs
Clks Rdiv Irefs Irclken Irefsten
ICS Control Register 1 ICSC1
ICSC1 Field Descriptions
Reference Divide Factor
ICSC2 Field Descriptions
ICS Control Register 2 ICSC2
ICS Trim Register Icstrm
Bdiv Range HGO Erefs Erclken Erefsten
Icssc Field Descriptions
ICS Status and Control Icssc
Icstrm Field Descriptions
DMX32 Irefst Clkst Oscinit FTRIM1 DRS
608 19.92 MHz
Reference range FLL factor DCO range
512 16 20 MHz
1024 32 40 MHz
IREFS=1 CLKS=00 IREFS=0
Operational Modes
FLL Engaged Internal FEI
IREFS=0 CLKS=10
FLL Bypassed Internal FBI
FLL Bypassed Internal Low Power Fbilp
FLL Engaged External FEE
FLL Bypassed External FBE
Bus Frequency Divider
Mode Switching
FLL Bypassed External Low Power Fbelp
Stop
Internal Reference Clock
Low Power Bit Usage
DCO Maximum Frequency with 32.768 kHz Oscillator
External Reference Clock
Fixed Frequency Clock
Local Clock
IIC1 Position Options
Module Configuration
Chapter Inter-Integrated Circuit S08IICV2
SOPT2IIC1PS
MCF51QE128 Series Block Diagram Highlighting the IIC Modules
Freescale Semiconductor 261
262 Freescale Semiconductor
SCL Serial Clock Line
SDA Serial Data Line
Freescale Semiconductor 263
Iica Field Descriptions
IIC Address Register Iica
IIC Frequency Divider Register Iicf
= Unimplemented or Reserved
Hold Times μs
Iicf Field Descriptions
Hold Time Values for 8 MHz Bus Speed
Mult ICR SDA
IIC Divider and Hold Values
ICR SCL
IIC Control Register IICC1
IICC1 Field Descriptions
IIC Status Register Iics
Iics Field Descriptions
TCF
Iicd Field Descriptions
IIC Data I/O Register Iicd
IIC Control Register 2 IICC2
Freescale Semiconductor 269
IIC Protocol
IICC2 Field Descriptions
Gcaen
Start Signal
Slave Address Transmission
Freescale Semiconductor 271
Arbitration Procedure
Stop Signal
Repeated Start Signal
Data Transfer
Clock Stretching
Clock Synchronization
Handshaking
Freescale Semiconductor 273
13.4.2 10-bit Address
Master-Transmitter Addresses a Slave-Receiver
Master-Receiver Addresses a Slave-Transmitter
Byte Transfer Interrupt
Resets
General Call Address
Address Detect Interrupt
276 Freescale Semiconductor
Module Initialization Master
Initialization/Application Information
Module Initialization Slave
Module Use
12. Typical IIC Interrupt Routine
Freescale Semiconductor 279
280 Freescale Semiconductor
RTC Clock Sources
Chapter Real-Time Counter S08RTCV1
ADC Hardware Trigger
RTC Modes of Operation
Interrupt Vector
MCF51QE128 Block Diagram Highlighting RTC Block and Pins
Freescale Semiconductor 283
Active Background Mode
Erclk
RTC Register Summary
LPO
Irclk
RTC Prescaler Divide-by values
RTC Status and Control Register Rtcsc
Rtcsc Field Descriptions
Rtif
Rtccnt Field Descriptions
RTC Counter Register Rtccnt
RTC Modulo Register Rtcmod
Rtcmod Field Descriptions
Rtcps
RTC Operation Example
Prescaler Period
KHz Internal Clock MHz External Clock Rtclks =
0x52 0x53 0x54 0x55 0x00 0x01
Internal 1-kHz Clock Source RTC Clock Rtcps =
Rtccnt Rtif
Freescale Semiconductor 289
290 Freescale Semiconductor
Chapter Serial Communications Interface S08SCIV4
SCI Clock Gating
Freescale Semiconductor 291
Serial Communications Interface S08SCIV4
Module Initialization
294 Freescale Semiconductor
Freescale Semiconductor 295
3shows the transmitter portion of the SCI
SCI Receiver Block Diagram
Freescale Semiconductor 297
SCI Baud Rate Registers SCIxBDH, SCIxBDL
SCIxBDH Field Descriptions
Lbkdie
Loops Sciswai Rsrc Wake ILT
SCI Control Register 1 SCIxC1
SCIxBDL Field Descriptions
Loops
SCI Control Register 2 SCIxC2
SCIxC2 Field Descriptions
TIE
SCI Status Register 1 SCIxS1
Tdre Rdrf Idle
Parity error
Framing error
No parity error
SCIxD
Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF
SCI Status Register 2 SCIxS2
SCIxS2 Field Descriptions
RXINV1
Txdir
SCI Control Register 3 SCIxC3
SCIxC3 Field Descriptions
TXINV1
SCI Data Register SCIxD
Baud Rate Generation
Freescale Semiconductor 305
Transmitter Functional Description
Send Break and Queued Idle
Break Character Length
Receiver Functional Description
Data Sampling Technique
BRK13
Receiver Wakeup Operation
Idle-Line Wakeup
Interrupts and Status Flags
Freescale Semiconductor 309
Additional SCI Functions
Stop Mode Operation
Loop Mode
15.3.5.1 8- and 9-Bit Data Modes
Single-Wire Operation
Freescale Semiconductor 311
312 Freescale Semiconductor
Chapter Serial Peripheral Interface S08SPIV3
SPI Clock Gating
Freescale Semiconductor 313
MCF51QE128 Block Diagram Highlighting SPI Block and Pins
Freescale Semiconductor 315
316 Freescale Semiconductor
Block Diagrams
SPI System Block Diagram
Freescale Semiconductor 317
SPI Module Block Diagram
SPI Baud Rate Generation
Freescale Semiconductor 319
Miso Master Data In, Slave Data Out
Spsck SPI Serial Clock
Mosi Master Data Out, Slave Data
SS Slave Select
SPI Control Register 1 SPIxC1
Modes of Operation
SPI in Stop Modes
SPIxC1 Field Descriptions
SS Pin Function
Master Mode Slave Mode
SPI Control Register 2 SPIxC2
Modfen Ssoe
SPIxC2 Register Field Descriptions
SPI Stop in Wait Mode
SPI Baud Rate Register SPIxBR
Modfen Bidiroe Spiswai
Sppr
SPI Status Register SPIxS
SPIxBR Register Field Descriptions
SPR
SPI Data Register SPIxD
SPI Clock Formats
10. SPI Clock Formats Cpha =
Freescale Semiconductor 327
SPI Interrupts
11. SPI Clock Formats Cpha =
Mode Fault Detection
Freescale Semiconductor 329
330 Freescale Semiconductor
Chapter Timer/Pulse-Width Modulator S08TPMV3
TPM Clock Gating
Freescale Semiconductor 331
Timer/Pulse-Width Modulator S08TPMV3
Freescale Semiconductor 333
334 Freescale Semiconductor
Freescale Semiconductor 335
336 Freescale Semiconductor
TPM Block Diagram
Freescale Semiconductor 337
Signal Description
Extclk
TPMxCHn TPM Channel n I/O Pins
Extclk External Clock Source
Freescale Semiconductor 339
High-True Pulse of an Edge-Aligned PWM
TOF Toie Cpwms Clksb Clksa PS2 PS1
TPM Status and Control Register TPMxSC
TPMxSC Field Descriptions
TOF
Prescale Factor Selection
TPM Counter Registers TPMxCNTHTPMxCNTL
TPM-Clock-Source Selection
Clksbclksa
TPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter
TPM Counter Modulo Registers TPMxMODHTPMxMODL
TPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter
Freescale Semiconductor 343
TPMxMOD70
TPM Channel n Status and Control Register TPMxCnSC
TPMxMOD158
CHnF CHnIE MSnB MSnA ELSnB ELSnA
Mode, Edge, and Level Selection
MSnBMSnA ELSnBELSnA Mode Configuration
TPMxCnSC Field Descriptions
Cpwms
TPMxCnV158
TPM Channel Value Registers TPMxCnVHTPMxCnVL
Mode, Edge, and Level Selection
TPMxCnV70
Counter
Counter Clock Source
Freescale Semiconductor 347
Counter Overflow and Modulo Reset
TPM Clock Source Selection
Input Capture Mode
Channel Mode Selection
Manual Counter Reset
Output Compare Mode
Edge-Aligned PWM Mode
15. PWM Period and Pulse Width ELSnA=0
Center-Aligned PWM Mode
Freescale Semiconductor 351
Reset Overview
Description of Reset Operation
General
Description of Interrupt Operation
Timer Overflow Interrupt TOF Description
Interrupt Local Source Description Enable
Interrupt Summary
Channel Event Interrupt Description
Center-Aligned PWM Case
Chapter Version 1 ColdFire Debug CF1DEBUG
Freescale Semiconductor 355
PST
Version 1 ColdFire Core CF1Core
OEP
Bkgd BDC
Revision
Modes of Operations
Debug Revision Summary
Csrhrl CSR2D1HRL
Core Status Command Set
BDM Command Types
Command Type Flash
BDM?
External Signal Descriptions
Debug Module Signals Description
BDM GO
DRc Register Name Width Access Reset Value Section Bits
Debug Module Memory Map
CPU
Configuration/Status Register CSR
CSR Field Descriptions
Bstat FOF TRG Halt Bkpt HRL BKD IPW
TRC DDC UHE BTB NPL IPI SSM FID DDH
TRC
Extended Configuration/Status Register Xcsr
Xcsr Reference Summary
Method Reference Details
Xcsr
CPU Cstat Halt Stop Eseqc Clksw SEC Erase Enbdm
Apcsc Apce
CPU State
Eseqc W
SEC R
Erase W
Xcsr CSR2
Configuration/Status Register 2 CSR2
CSR2 Reference Summary
Syncpc Interval
CSR2 Field Descriptions
PSTBWA7
Pstb Valid Data Locations Oldest to Newest
Pstbss
Configuration/Status Register 3 CSR3
10. CSR3 Reference Summary
Start Condition Stop Condition
BDM Address Attribute Register Baar
BFC Bfcdiv DIV8
BFCDIV8
Address Attribute Trigger Register Aatr
SZM TTM TMM
Trigger Definition Register TDR
Signal of the processor’s local bus
BDM memory commands Normal processor access Else Reserved
SZM
L2T L1T
L2ED
L2EA
L1EA
L2T
Three bits disables the address breakpoint
Program Counter Breakpoint/Mask Registers PBR0-3, Pbmr
No inversion Invert data breakpoint comparators
DRc 0x08 PBR0
Mask Reset
15. PBR0 Field Descriptions
DRc 0x09 Pbmr
Abhr
Address Breakpoint Registers ABLR, Abhr
17. Pbmr Field Descriptions
Ablr
Data Breakpoint and Mask Registers DBR, Dbmr
19. Abhr Field Description
21. Dbmr Field Descriptions
Address1 Access Size Operand Location
Background Debug Mode BDM
22. Access Size and Operand Data Location
Resulting Set of Possible Trigger Combinations
Halt Source Halt Timing Description
CPU Halt
23. CPU Halt Sources
Cpucrard =
Cpucrird =
Background Debug Serial Interface Controller BDC
BDM Communication Details
15. BDC Host-to-Target Serial Bit Timing
Freescale Semiconductor 385
16. BDC Target-to-Host Serial Bit Timing Logic
BDM Command Set Descriptions
Freescale Semiconductor 387
Core Register Commands
Miscellaneous Commands
Memory Commands
PST Trace Buffer Read Commands
CRG CRN
24. BDM Command Code Field Descriptions
CRG
VBR
Ackdisable
BDM Command Set Summary
25. BDM Command Summary
Ackenable
Readcreg
Readdreg
Readpstb
Syncpc
Writecreg
0x03
Disable host/target handshake protocol Always Available
Enable host/target handshake protocol Always Available
Freescale Semiconductor 393
Data7-0
Enter active background mode if enabled Non-intrusive
0x32 Host → Target Memory data7-0 Target → 0x36
0x3A Memory
0x37
0x33
Xcsrsb
0x3B
0x12 Memory
0x12 Memory data7-0
Target 0x16 Memory Data15-8 Memory data7-0
Target → Host 0x16 Memory
No operation Non-intrusive
Read CPU control register Active Background
0x30 Address23-0
Read debug control register Non-intrusive
0xA0+CRN Host → Target Dreg data
Target Memory data7-0 Target → Host
0x39
0x31
0x35
0x50+CRN Host → Target Pstb data
Read CSR2 Status Byte Always Available
Read general-purpose CPU register Active Background
Read Xcsr Status Byte Always Available
Read CSR3 Status Byte Always Available
0xC0+CRN Creg data
Synchronize PC to PST/DDATA Signals Non-intrusive
Write CPU control register Active Background
Freescale Semiconductor 401
0x10 Address23-0 Memory Data7-0
Write debug control register Non-intrusive
0x80+CRN Dreg data
Host → target
Write general-purpose CPU register Active Background
Write CSR2 Status Byte Always Available
Serial Interface Hardware Handshake Protocol
Write Xcsr Status Byte Always Available
Write CSR3 Status Byte Always Available
19. Target Acknowledge Pulse ACK
Freescale Semiconductor 405
Hardware Handshake Abort Procedure
20. Handshake Protocol at Command Level
21signal timing is not drawn to scale
Freescale Semiconductor 407
21. ACK Abort Procedure at the Command Level
Real-Time Debug Support
Real-Time Trace Support
Freescale Semiconductor 409
PST40 Definition
Enter user mode
26. Processor Status Encodings
Instructions, generate different encodings
Begin Execution of Taken Branch PST =
0x08-0x0B
Freescale Semiconductor 411
23. Example JMP Instruction Output in Pstb
PST Values Description
Pstbpst
PST Trace Buffer Pstb
18.4.3.3 PST/DDATA Example
Pstbddata
Processor Status, Debug Data Definition
PST/DDATA
27. PST/DDATA Specification for User-Mode Instructions
Instruction Operand Syntax
Freescale Semiconductor 415
416 Freescale Semiconductor
Freescale Semiconductor 417
Supervisor Instruction Set
No Connect
GND Reset
Freescale-Recommended BDM Pinout
Freescale Semiconductor 419
420 Freescale Semiconductor
MCF51QE128RM Rev to Rev Changes
Appendix a Revision History
Changes between Rev and Rev
Chapter Description
Revision History
Page
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