Freescale Semiconductor MCF51QE128RM manual Port F Registers, Port F Data Register Ptfd

Chapter 6 Parallel Input/Output Control

6.7.6Port F Registers

Port F is controlled by the registers listed below.

6.7.6.1Port F Data Register (PTFD)

R

W

Reset:

7	6	5	4	3	2	1	0
PTFD7	PTFD6	PTFD5	PTFD4	PTFD3	PTFD2	PTFD1	PTFD0
0	0	0	0	0	0	0	0

Figure 6-35. Port F Data Register (PTFD)

	Table 6-32. PTFD Register Field Descriptions
Field	Description
7–0	Port F Data Register Bits. For port F pins configured as inputs, reads return the logic level on the pin. For port F
PTFDn	pins configured as outputs, reads return the last value written to this register.
	Writes are latched into all bits of this register. For port F pins configured as outputs, the logic level is driven out
	the corresponding MCU pin.
	Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
	all port pins as high-impedance inputs with pull-ups disabled.

6.7.6.2Port F Data Direction Register (PTFDD)

R

W

Reset:

7	6	5	4	3	2	1	0
PTFDD7	PTFDD6	PTFDD5	PTFDD4	PTFDD3	PTFDD2	PTFDD1	PTFDD0
0	0	0	0	0	0	0	0

		Figure 6-36. Port F Data Direction Register (PTFDD)
		Table 6-33. PTFDD Register Field Descriptions
Field		Description
7–0	Data Direction for Port F Bits. These read/write bits control the direction of port F pins and what is read for PTFD
PTFDDn	reads.
	0	Input (output driver disabled) and reads return the pin value.
	1	Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.

6.7.6.3Port F Pull Enable Register (PTFPE)

The port F pull enable register enables pull-ups on the corresponding PTF pin. In some cases, a pull-down device is enabled if pull-downs are supported by an alternate pin function (e.g., KBI).

MCF51QE128 MCU Series Reference Manual, Rev. 3

132 Freescale Semiconductor

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