MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 175
Get the latest version from freescale.com
Chapter 8 Interrupt Controller (CF1_INTC)
type determines whether the program counter placed in the exception stack frame defines the
location of the faulting instruction (fault) or the address of the next instruction to be executed
(next). For interrupts, the stacked PC is always the address of the next instruction to be executed.
• The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1-Mbyte boundary. This instruction address is generated
by fetching a 32-bit exception vector from the table located at the address defined in the vector base
register (VBR). The index into the exception table is calculated as (4 ×vector number). After the
exception vector has been fetched, the contents of the vector serves as a 32-bit pointer to the
address of the first instruction of the desired handler. After the instruction fetch for the first opcode
of the handler has been initiated, exception processing terminates and normal instruction
processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address boundary. For
the V1 ColdFire core, the only practical locations for the vector table are based at 0x(00)00_0000 in the
flash or 0x(00)80_0000 in the RAM. The table contains 256 exception vectors; the first 64 are reserved for
internal processor exceptions, and the remaining 192 are user-defined interrupt vectors. For the V1
ColdFire core, the table is partially populated with the first 64 reserved for internal processor exceptions,
while vectors 64 – 102 are reserved for the peripheral I/O requests and the seven software interrupts. The
IRQ assignments are device-specific as they depend on the exact set of peripherals for any given device.
A simplified V1 ColdFire exception vector table is shown in Table 8-2 .
Table 8-2. V1 ColdFire Exception Vector Table
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
0 0x000 — Initial supervisor stack pointer
1 0x004 — Initial program counter
2–63 0x008–0x0FC — Reserved for internal CPU
exceptions
64 0x100 Next IRQ_pin
65 0x104 Next Low_voltage
66 0x108 Next TPM1_ch0
67 0x10C Next TPM1_ch1
68 0x110 Next TPM1_ch2
69 0x114 Next TPM1_ovfl
70 0x118 Next TPM2_ch0
71 0x11C Next TPM2_ch1
72 0x120 Next TPM2_ch2
73 0x124 Next TPM2_ovfl
74 0x128 Next SPI2
75 0x12C Next SPI1
76 0x130 Next SCI1_err