SCIxC2 Field Descriptions | Freescale Semiconductor MCF51QE128RM

		Table 15-3. SCIxC1 Field Descriptions (continued)

Field		Description

1	Parity Enable. Enables hardware parity generation and checking. When parity is enabled, the most significant bit
PE	(msb) of the data character (eighth or ninth data bit) is treated as the parity bit.
	0	No hardware parity generation or checking.
	1	Parity enabled.

0	Parity Type. Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
PT	number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
	the data character, including the parity bit, is even.
	0	Even parity.
	1	Odd parity.

15.2.3SCI Control Register 2 (SCIxC2)

This register can be read or written at any time.

R

W

Reset

7	6	5	4	3	2	1	0
TIE	TCIE	RIE	ILIE	TE	RE	RWU	SBK

0	0	0	0	0	0	0	0

		Figure 15-8. SCI Control Register 2 (SCIxC2)
		Table 15-4. SCIxC2 Field Descriptions

Field		Description

7	Transmit Interrupt Enable (for TDRE)
TIE	0	Hardware interrupts from TDRE disabled (use polling).
	1	Hardware interrupt requested when TDRE flag is 1.

6	Transmission Complete Interrupt Enable (for TC)
TCIE	0	Hardware interrupts from TC disabled (use polling).
	1	Hardware interrupt requested when TC flag is 1.

5	Receiver Interrupt Enable (for RDRF)
RIE	0	Hardware interrupts from RDRF disabled (use polling).
	1	Hardware interrupt requested when RDRF flag is 1.

4	Idle Line Interrupt Enable (for IDLE)
ILIE	0	Hardware interrupts from IDLE disabled (use polling).
	1	Hardware interrupt requested when IDLE flag is 1.

3	Transmitter Enable
TE	0	Transmitter off.
	1	Transmitter on.
	TE must be 1 to use the SCI transmitter. When TE is set, the SCI forces the TxD pin to act as an output for the
	SCI system.
	When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
	traffic on the single SCI communication line (TxD pin).
	TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress. Refer to
	Section 15.3.2.1, “Send Break and Queued Idle” for more details.
	When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
	break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.

		MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual SCI Control Register 2 SCIxC2, SCIxC2 Field Descriptions, Tie

Contents

MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Chapter Resets, Interrupts, and General System Control Freescale Semiconductor Title Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Section Number Title Chapter Inter-Integrated Circuit S08IICV2 Real-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History MCF51QE128 Series Features by MCU and Package Feature MCF51QE128Chapter Device Overview Devices in the MCF51QE128/64/32 Series MCU Block Diagram Xosc MCF51QE128/64/32 Block Diagram V1 ColdFire Core System ClocksInternal Clock Source ICS Module Module Versions Simplified ICS Block Diagram System Clock Distribution Icsirclk FLL Bypassed Internal Low-Power Fbilp ICS Modes of OperationFLL Engaged Internal FEI FLL Engaged External FEE FLL Bypassed External Low-Power Fbelp Stop Stop Get the latest version from freescale.com Get the latest version from freescale.com Chapter Pins and Connections Device Pin Assignment Pins in bold are added from the next smaller package Pin Lqfp Recommended System Connections Basic System Connections Power Reset and RstoOscillator Background / Mode Select BKGD/MS ADC Reference Pins VREFH, Vrefl General-Purpose I/O and Peripheral Ports Pin Assignment by Package and Pin Sharing Priority PinPriority Number Port Pin Alt Number Port Pin Alt Get the latest version from freescale.com Features Chapter Modes of OperationIntroduction MCF51QE128/64/32 Power Modes Conceptual Drawing Overview CPU / Power Mode Selections PMC Mode Regulator State Stop3Full On Run Stop2 LPrun Triggers for Transitions Shown in Figure Transition # From Trigger Debug Mode Secure Mode Run Mode Low-Power Run Mode LPrunBDM in Low-Power Run Mode Run Modes Wait Mode Low-Power Wait Mode LPwaitBDM in Low-Power Wait Mode Wait Modes Stop2 Mode Stop3 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop ModeLow-Range Oscillator Considerations for Stop2 On-Chip Peripheral Modules in Stop and Low-Power Modes Low-Power Mode BehaviorAbbreviations used in Table CF1CORE BDC COPICS IRQ Get the latest version from freescale.com Get the latest version from freescale.com Chapter Memory MCF51QE128/64/32 Memory MapKbytes RAM CPU Access Type Allowed by Region Register Addresses and Bit AssignmentsRead Write Base Address Region Byte Long Byte ColdFire Memory Organization Direct-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 2 Register Address Name Direct-Page Register Summary Sheet 3 Direct-Page Register Summary Sheet 4 High-Page Register Summary Sheet 1 High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 Flash Module Reserved Memory Locations High-Page Register Summary Sheet 5Reserved Flash Memory Addresses 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x00000408 0x0000040CReserved Flash Memory Addresses Register Nvprot ColdFire Rapid Gpio Memory Map ColdFire Interrupt Controller Memory MapV1 ColdFire Rapid Gpio Memory Map V1 ColdFire Interrupt Controller Memory Map RAM FlashIntcsfrc Intccfrc Features Lov-Voltage Programming Sequence ExampleAddresses Desired Value Values Programmed Register Descriptions Flash Clock Divider Register FcdivFlash Options Register Fopt and Nvopt Fcdiv Field Descriptions Flash Configuration Register Fcnfg 10. Fopt Field Descriptions Flash Protection Register Fprot and Nvprot 11. Fcnfg Field Descriptions12. Fprot Field Descriptions 13. Flash Protection Address Range 0x00-0x3F 0x400x41 0x00000-0x1EFFF 0x42 Command buffers are full Flash Status Register FstatFcbef Fccf Fpviol Faccerr Fblank W1c Flash Command Operations Flash Command Register FcmdFunction Description 15. Fcmd Field Descriptions Writing the Fcdiv Register 200 195 ⎟ 200 = 3% Command Write Sequence Commands ImpossibleStart ALL Program and Erase Flash Commands Erase Verify Command16. Flash Command Description Fcmd NVM Program Command 11. Example Program Command Flow Burst Program Command Sector Erase Command Command Buffer EmptySequential Programming 13. Example Sector Erase Command Flow Mass Erase Command 14. Example Mass Erase Command Flow Flash Access Violations Illegal Flash Operations Wait Mode Background Debug ModeOperating Modes Flash Protection Violations Unsecuring the MCU using Backdoor Key Access Security Resets Flash Reset SequenceReset While Flash Command Active Program and Erase Times Security Sync Set PRDIV8 and clock divider fields in CSR3Stop Device is unsecure Chapter Resets, Interrupts, and General System Control Microcontroller Reset COP Configuration Options Computer Operating Properly COP WatchdogControl Bits Clock Source COP Overflow Count Copclks Copt Illegal Operation Reset Illegal Address ResetPin Configuration Options Interrupts and Exceptions Power-On Reset Operation Low-Voltage Detect LVD SystemEdge and Level Sensitivity External Interrupt Initialization LVD Reset Operation Peripheral Clock GatingLVD Interrupt Operation Low-Voltage Warning LVW Interrupt Operation Interrupt Pin Request Status and Control Register Irqsc Irqsc Register Field DescriptionsIrqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack Irqpdd System Reset Status Register SRS POR System Options Register 1 SOPT1 POR LVR System Options Register 2 SOPT2 SOPT1 Register Field Descriptions System Device Identification Register SDIDH, Sdidl SOPT2 Register Field DescriptionsSPI1PS SPSCLK1 MOSI1 MISO1 SS1 IIC1PS SDA1 SCL1 Sdidh Register Field Descriptions Sdidl Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack SPMSC1 Register Field Descriptions LPR Lprs Lpwui Ppde Ppdc Ppdack SPMSC2 Register Field Descriptions 11. LVD and LVW Trip Point Typical Values1 Lvwf Lvdv Lvwv LvwieLvwf Lvdvlvwv System Clock Gating Control 1 Register SCGC1 System Clock Gating Control 2 Register SCGC212. SCGC1 Register Field Descriptions TPM3 13. SCGC2 Register Field Descriptions RTC SPI2 SPI1FLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Chapter Parallel Input/Output Control Port Data and Data DirectionFreescale Semiconductor 113 Port Internal Pull-up Enable Port Slew Rate EnablePull-up, Slew Rate, and Drive Strength Data Direction Control Port Data Register Port Read Port Data Set, Clear and Toggle Data Registers Port Drive Strength SelectFreescale Semiconductor 115 V1 ColdFire Rapid Gpio Functionality Keyboard InterruptsPort Data Set Registers Port Data Clear Registers Edge Only Sensitivity Edge and Level SensitivityPull-up/Pull-down Resistors Freescale Semiconductor 117 Pin Behavior in Stop Modes Parallel I/O, Keyboard Interrupt, and Pin Control RegistersKeyboard Interrupt Initialization Port a Registers Port a Pull Enable Register Ptape Port a Data Register PtadPort a Data Direction Register Ptadd PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0 Port a Slew Rate Enable Register Ptase Port a Drive Strength Selection Register PtadsPTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 Port B Registers Port B Data Register PtbdPort B Data Direction Register Ptbdd Ptads Register Field Descriptions Port B Pull Enable Register Ptbpe Port B Slew Rate Enable Register PtbsePtbdd Register Field Descriptions Ptbpe Register Field Descriptions Port C Registers Port B Drive Strength Selection Register PtbdsPort C Data Register Ptcd 10. Ptbds Register Field Descriptions Port C Data Direction Register Ptcdd Port C Data Set Register PtcsetPort C Data Clear Register Ptcclr 12. Ptcdd Register Field Descriptions Port C Pull Enable Register Ptcpe Port C Toggle Register Ptctog14. Ptcclr Register Field Descriptions 16. Ptcpe Register Field Descriptions Port C Slew Rate Enable Register Ptcse Port D RegistersPort C Drive Strength Selection Register Ptcds Port D Data Register Ptdd Port D Pull Enable Register Ptdpe Port D Data Direction Register Ptddd19. Ptdd Register Field Descriptions 20. Ptddd Register Field Descriptions Port D Slew Rate Enable Register Ptdse Port E RegistersPort D Drive Strength Selection Register Ptdds Port E Data Register Pted Port E Data Direction Register Ptedd Port E Data Set Register Pteset24. Pted Register Field Descriptions 25. Ptedd Register Field Descriptions Port E Pull Enable Register Ptepe Port E Data Clear Register PteclrPort E Toggle Register Ptetog PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 Port E Slew Rate Enable Register Ptese Port E Drive Strength Selection Register Pteds29. Ptepe Register Field Descriptions 30. Ptese Register Field Descriptions Port F Pull Enable Register Ptfpe Port F RegistersPort F Data Register Ptfd Port F Data Direction Register Ptfdd Port F Slew Rate Enable Register Ptfse Port F Drive Strength Selection Register Ptfds34. Ptfpe Register Field Descriptions 35. Ptfse Register Field Descriptions Port G Registers Port G Data Register PtgdPort G Data Direction Register Ptgdd 36. Ptfds Register Field Descriptions Port G Pull Enable Register Ptgpe Port G Slew Rate Enable Register PtgsePort G Drive Strength Selection Register Ptgds 39. Ptgpe Register Field Descriptions Port H Registers Port H Data Register PthdPort H Data Direction Register Pthdd 41. Ptgds Register Field Descriptions Port H Pull Enable Register Pthpe Port H Slew Rate Enable Register PthsePort H Drive Strength Selection Register Pthds 44. Pthpe Register Field Descriptions Port J Registers Port J Data Register PtjdPort J Data Direction Register Ptjdd Port J Pull Enable Register Ptjpe Port J Slew Rate Enable Register PtjsePort J Drive Strength Selection Register Ptjds 49. Ptjpe Register Field Descriptions Keyboard Interrupt 1 KBI1 Registers 10.1 KBI1 Interrupt Status and Control Register KBI1SC51. Ptjds Register Field Descriptions 52. KBI1 Pin Mapping Keyboard Interrupt 1 KBI2 Registers 10.2 KBI1 Interrupt Pin Select Register KBI1PE10.3 KBI1 Interrupt Edge Select Register KBI1ES 11.1 KBI2 Interrupt Status and Control Register KBI2SC 11.2 KBI2 Interrupt Pin Select Register KBI2PE57. KBI2SC Register Field Descriptions 58. KBI2PE Register Field Descriptions 11.3 KBI2 Interrupt Edge Select Register KBI2ES 59. KBI2ES Register Field DescriptionsFreescale Semiconductor 143 144 Freescale Semiconductor Chapter ColdFire Core Overview Memory Map/Register Description Supervisor/User Access Registers Supervisor Access Only RegistersData Registers D0-D7 ColdFire Core Programming Model Address Registers A0-A6 Supervisor/User Stack Pointers A7 and OTHERA7Data Condition Code Register CCR Freescale Semiconductor 149 Program Counter PC Vector Base Register VBRCCR Field Descriptions CPU Configuration Register Cpucr Status Register SR SR Field DescriptionsBWD Functional Description Instruction Set Architecture IsacInstruction Enhancements over Revision Isaa Instruction Description Exception Processing Overview Exception Vector Assignments Vector StackedAssignment Numbers Offset Hex Counter Exception Stack Frame Definition AssignmentNumbers Offset Hex Counter SSP → Fault Status Encodings 2.2 S08 and ColdFire Exception Processing ComparisonFormat Field Encodings FS30 Definition Exception Processing Comparison Attribute S08 V1 ColdFireRTI RTE Access Error Exception Address Error ExceptionProcessor Exceptions Freescale Semiconductor 159 Illegal Instruction Exception 10. ColdFire Opword Line DefinitionLine OpMode Effective Address OpwordLine Instruction Class Privilege Violation Trace ExceptionFreescale Semiconductor 161 RTE and Format Error Exception Unimplemented Line-A OpcodeUnimplemented Line-F Opcode Debug Interrupt Fault-on-Fault Halt Trap Instruction ExceptionUnsupported Instruction Exception Interrupt Exception Reset Exception Access User read-only BDM read-onlyBDM Load 0x60 D0 Store 0x40 D0 VER REV 11. D0 Hardware Configuration Info Field Description 12. D1 Hardware Configuration Information Field Description FlashszSramsz Instruction Execution Timing Timing Assumptions13. Misaligned Operand References Address10 Size Bus Additional Operations CR/W Move Instruction Execution Times 14. Move Byte and Word Execution Times15. Move Long Execution Times Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl Standard One Operand Instruction Execution Times 16. One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Standard Two Operand Instruction Execution Times 17. Two Operand Instruction Execution Times Miscellaneous Instruction Execution Times 18. Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Branch Instruction Execution Times 19. General Branch Instruction Execution Times20. Bcc Instruction Execution Times Chapter Interrupt Controller CF1INTC AttributeHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x144 0x148 Next ACMPx 0x14C0x150 Next SCI2rx 0x154 SCI2tx 0x158 0x180 Next Interrupt Source Number To V1 ColdFire coreFreescale Semiconductor 177 External Signal Description Memory Map and Register DefinitionModes of Operation Memory Map Intc Force Interrupt Register IntcfrcCF1INTC Memory Map Intcfrc Field Descriptions Intc Wake-up Control Register Intcwcr INTCPL6P7,6 Field DescriptionsFreescale Semiconductor 181 Intc Set Interrupt Force Register Intcsfrc Intcwcr Field DescriptionsENB Intc Clear Interrupt Force Register Intccfrc Intcsfrc Field DescriptionsIntccfrc Field Descriptions Offset CF1INTCBASE + 0x1F Intccfrc Intc Software and Level-nIACK Registers n = 1,2,3,...,7 Vecn Swiack Interrupt Request Level and Priority Assignments INTCSWIACK, INTCLVLnIACK Field Descriptions10. Legend for Table Priority within Level Midpoint 12. V1 ColdFire Interrupt Assignments TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovflTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Initialization Information Application InformationEmulation of the HCS08’s 1-Level IRQ Handling Using INTCPL6P7,6 Registers More on Software IACKsFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Chapter Rapid Gpio Rgpio Freescale Semiconductor 193 V1 ColdFire Core Freescale Semiconductor 195 IFP CoreOEP Dsoc RAM Rgpio Rgpio ModulePin Muxing + Pad Logic On-platform Bus RGPIODATA150 Detailed Signal Descriptions Rgpio Module External I/O SignalsRgpio Detailed Signal Descriptions Memory Map/Register Definition Rgpio Write Memory MapRgpio Read Memory Map Rgpio Data Direction Rgpiodir Rgpio Data RgpiodataRgpiodir Field Descriptions DIR Rgpio Pin Enable Rgpioenb Rgpio Clear Data Rgpioclr Rgpio Set Data Rgpioset Rgpio Toggle Data RgpiotogRgpioclr Field Descriptions Rgpioset Field Descriptions Application 1 Simple Square-Wave Generation 10. Rgpiotog Field DescriptionsTOG Field Description 15-0 Rgpio Toggle Data 11. Square-Wave Output Performance 12. Emulated SPI Performance using Gpio Outputs SPI Speed @ Relative CPU f = 50 MHz29x Freescale Semiconductor 205 206 Freescale Semiconductor Acmp Configuration Information ACMP/TPM Configuration InformationChapter Analog Comparator 3V ACMPVLPV1 Acmp Clock Gating Interrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Block Diagram Wait Mode OperationStop3 Mode Operation Stop2 Mode Operation Register Definition Status and Control Register ACMPxSCAcbgs Acpe Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF Interrupts ACMPxSC Field DescriptionsAcme Acmod 214 Freescale Semiconductor Chapter Analog-to-Digital Converter S08ADC12V1 ADC Clock GatingFreescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 Module Configurations Channel AssignmentsAlternate Clock ADC Channel Assignment Temperature Sensor Hardware Trigger 2provides a block diagram of the ADC module Freescale Semiconductor 219 Signal Properties Name FunctionAD27-AD0 Analog Power Vddad Analog Ground VssadVoltage Reference High Vrefh Voltage Reference Low Vrefl Coco Input Channel SelectInput Select Status and Control Register 2 ADCSC2 Data Result High Register AdcrhADCSC2 Register Field Descriptions Adact Data Result Low Register Adcrl Compare Value High Register AdccvhADR10 ADR9 ADR8 ADCV11 ADCV10 ADCV9 ADCV8 Configuration Register Adccfg Compare Value Low Register AdccvlAdccfg Register Field Descriptions Adlpc Pin Control 1 Register APCTL1 Clock Divide SelectConversion Modes Input Clock Select Pin Control 2 Register APCTL2 10. APCTL1 Register Field DescriptionsADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 Pin Control 3 Register APCTL3 11. APCTL2 Register Field DescriptionsADPC15 ADPC23 12. APCTL3 Register Field Descriptions ADPC21ADPC20 ADPC16 Clock Select and Divide Control Input Select and Pin ControlHardware Trigger Conversion Control Initiating Conversions Completing ConversionsAborting Conversions Freescale Semiconductor 231 Power Control Sample Time and Total Conversion Time13. Total Conversion Time vs. Control Conditions Adiclk Adlsmp MCU Wait Mode Operation Automatic Compare Function MCU Stop3 Mode Operation MCU Stop2 Mode OperationStop3 Mode With Adack Disabled Stop3 Mode With Adack Enabled ADC Module Initialization Example Initialization SequencePseudo-Code Example Freescale Semiconductor 235 External Pins and Routing Reset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check NoCOCO=1? Yes Read Adcrh Then Adcrl To Clear Coco Bit Continue Analog Supply Pins Analog Reference PinsAnalog Input Pins Freescale Semiconductor 237 Sources of Error Sampling ErrorPin Leakage Error Noise-Induced Errors Code Width and Quantization Error Linearity ErrorsLsb = Freescale Semiconductor 239 Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor Stop2 Mode Considerations Chapter Internal Clock Source S08ICSV3External Oscillator Freescale Semiconductor 243 Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor HGO, RANGE, EREFS, ERCLKEN, Erefsten Freescale Semiconductor 247 2is the ICS block diagram FLL Bypassed Internal Low Power Fbilp FLL Bypassed External Low Power FbelpICS Register Summary Rdiv Irefs ICS Control Register 1 ICSC1 ICSC1 Field DescriptionsClks Rdiv Irefs Irclken Irefsten Reference Divide Factor ICS Control Register 2 ICSC2 ICS Trim Register IcstrmICSC2 Field Descriptions Bdiv Range HGO Erefs Erclken Erefsten ICS Status and Control Icssc Icstrm Field DescriptionsIcssc Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRS Reference range FLL factor DCO range 512 16 20 MHz608 19.92 MHz 1024 32 40 MHz Operational Modes FLL Engaged Internal FEIIREFS=1 CLKS=00 IREFS=0 IREFS=0 CLKS=10 FLL Bypassed Internal Low Power Fbilp FLL Engaged External FEEFLL Bypassed Internal FBI FLL Bypassed External FBE Mode Switching FLL Bypassed External Low Power FbelpBus Frequency Divider Stop Low Power Bit Usage DCO Maximum Frequency with 32.768 kHz OscillatorInternal Reference Clock External Reference Clock Fixed Frequency Clock Local Clock Module Configuration Chapter Inter-Integrated Circuit S08IICV2IIC1 Position Options SOPT2IIC1PS MCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SCL Serial Clock Line SDA Serial Data LineFreescale Semiconductor 263 IIC Address Register Iica IIC Frequency Divider Register IicfIica Field Descriptions = Unimplemented or Reserved Iicf Field Descriptions Hold Time Values for 8 MHz Bus SpeedHold Times μs Mult ICR SDA IIC Divider and Hold Values ICR SCL IIC Control Register IICC1 IICC1 Field Descriptions IIC Status Register Iics Iics Field DescriptionsTCF IIC Data I/O Register Iicd IIC Control Register 2 IICC2Iicd Field Descriptions Freescale Semiconductor 269 IIC Protocol IICC2 Field DescriptionsGcaen Start Signal Slave Address TransmissionFreescale Semiconductor 271 Stop Signal Repeated Start SignalArbitration Procedure Data Transfer Clock Synchronization HandshakingClock Stretching Freescale Semiconductor 273 13.4.2 10-bit Address Master-Transmitter Addresses a Slave-ReceiverMaster-Receiver Addresses a Slave-Transmitter Resets General Call AddressByte Transfer Interrupt Address Detect Interrupt 276 Freescale Semiconductor Initialization/Application Information Module Initialization SlaveModule Initialization Master Module Use 12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor Chapter Real-Time Counter S08RTCV1 ADC Hardware TriggerRTC Clock Sources RTC Modes of Operation Interrupt Vector MCF51QE128 Block Diagram Highlighting RTC Block and Pins Freescale Semiconductor 283 Active Background Mode RTC Register Summary LPOErclk Irclk RTC Status and Control Register Rtcsc Rtcsc Field DescriptionsRTC Prescaler Divide-by values Rtif RTC Counter Register Rtccnt RTC Modulo Register RtcmodRtccnt Field Descriptions Rtcmod Field Descriptions RTC Operation Example Prescaler PeriodRtcps KHz Internal Clock MHz External Clock Rtclks = Internal 1-kHz Clock Source RTC Clock Rtcps = Rtccnt Rtif0x52 0x53 0x54 0x55 0x00 0x01 Freescale Semiconductor 289 290 Freescale Semiconductor Chapter Serial Communications Interface S08SCIV4 SCI Clock GatingFreescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI SCI Receiver Block Diagram Freescale Semiconductor 297 SCI Baud Rate Registers SCIxBDH, SCIxBDL SCIxBDH Field DescriptionsLbkdie SCI Control Register 1 SCIxC1 SCIxBDL Field DescriptionsLoops Sciswai Rsrc Wake ILT Loops SCI Control Register 2 SCIxC2 SCIxC2 Field DescriptionsTIE SCI Status Register 1 SCIxS1 Tdre Rdrf Idle Framing error No parity errorParity error SCIxD SCI Status Register 2 SCIxS2 SCIxS2 Field DescriptionsLbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF RXINV1 SCI Control Register 3 SCIxC3 SCIxC3 Field DescriptionsTxdir TXINV1 SCI Data Register SCIxD Baud Rate GenerationFreescale Semiconductor 305 Transmitter Functional Description Send Break and Queued Idle Receiver Functional Description Data Sampling TechniqueBreak Character Length BRK13 Receiver Wakeup Operation Idle-Line Wakeup Interrupts and Status Flags Freescale Semiconductor 309 Stop Mode Operation Loop ModeAdditional SCI Functions 15.3.5.1 8- and 9-Bit Data Modes Single-Wire Operation Freescale Semiconductor 311 312 Freescale Semiconductor Chapter Serial Peripheral Interface S08SPIV3 SPI Clock GatingFreescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor Block Diagrams SPI System Block DiagramFreescale Semiconductor 317 SPI Module Block Diagram SPI Baud Rate Generation Freescale Semiconductor 319 Spsck SPI Serial Clock Mosi Master Data Out, Slave DataMiso Master Data In, Slave Data Out SS Slave Select Modes of Operation SPI in Stop ModesSPI Control Register 1 SPIxC1 SPIxC1 Field Descriptions Master Mode Slave Mode SPI Control Register 2 SPIxC2SS Pin Function Modfen Ssoe SPI Stop in Wait Mode SPI Baud Rate Register SPIxBRSPIxC2 Register Field Descriptions Modfen Bidiroe Spiswai SPI Status Register SPIxS SPIxBR Register Field DescriptionsSppr SPR SPI Data Register SPIxD SPI Clock Formats 10. SPI Clock Formats Cpha = Freescale Semiconductor 327 SPI Interrupts 11. SPI Clock Formats Cpha = Mode Fault Detection Freescale Semiconductor 329 330 Freescale Semiconductor Chapter Timer/Pulse-Width Modulator S08TPMV3 TPM Clock GatingFreescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor TPM Block Diagram Freescale Semiconductor 337 Signal Description Extclk TPMxCHn TPM Channel n I/O Pins Extclk External Clock SourceFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TPM Status and Control Register TPMxSC TPMxSC Field DescriptionsTOF Toie Cpwms Clksb Clksa PS2 PS1 TOF TPM Counter Registers TPMxCNTHTPMxCNTL TPM-Clock-Source SelectionPrescale Factor Selection Clksbclksa TPM Counter Modulo Registers TPMxMODHTPMxMODL TPMxCNT158 Any write to TPMxCNTH clears the 16-bit counterTPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter Freescale Semiconductor 343 TPM Channel n Status and Control Register TPMxCnSC TPMxMOD158TPMxMOD70 CHnF CHnIE MSnB MSnA ELSnB ELSnA MSnBMSnA ELSnBELSnA Mode Configuration TPMxCnSC Field DescriptionsMode, Edge, and Level Selection Cpwms TPM Channel Value Registers TPMxCnVHTPMxCnVL Mode, Edge, and Level SelectionTPMxCnV158 TPMxCnV70 Counter Counter Clock SourceFreescale Semiconductor 347 Counter Overflow and Modulo Reset TPM Clock Source Selection Channel Mode Selection Manual Counter ResetInput Capture Mode Output Compare Mode Edge-Aligned PWM Mode 15. PWM Period and Pulse Width ELSnA=0 Center-Aligned PWM Mode Freescale Semiconductor 351 Reset Overview Description of Reset OperationGeneral Timer Overflow Interrupt TOF Description Interrupt Local Source Description EnableDescription of Interrupt Operation Interrupt Summary Channel Event Interrupt Description Center-Aligned PWM Case Chapter Version 1 ColdFire Debug CF1DEBUG Freescale Semiconductor 355 Version 1 ColdFire Core CF1Core OEPPST Bkgd BDC Modes of Operations Debug Revision SummaryRevision Csrhrl CSR2D1HRL BDM Command Types Command Type FlashCore Status Command Set BDM? External Signal Descriptions Debug Module Signals DescriptionBDM GO DRc Register Name Width Access Reset Value Section Bits Debug Module Memory MapCPU Configuration/Status Register CSR CSR Field Descriptions Bstat FOF TRG Halt Bkpt HRL BKD IPWTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Extended Configuration/Status Register Xcsr Xcsr Reference SummaryMethod Reference Details CPU Cstat Halt Stop Eseqc Clksw SEC Erase Enbdm Apcsc ApceXcsr CPU State Eseqc W SEC RErase W Configuration/Status Register 2 CSR2 CSR2 Reference SummaryXcsr CSR2 Syncpc Interval CSR2 Field Descriptions PSTBWA7 Pstb Valid Data Locations Oldest to Newest Configuration/Status Register 3 CSR3 10. CSR3 Reference SummaryPstbss Start Condition Stop Condition BDM Address Attribute Register Baar BFC Bfcdiv DIV8BFCDIV8 Address Attribute Trigger Register Aatr SZM TTM TMM Signal of the processor’s local bus BDM memory commands Normal processor access Else ReservedTrigger Definition Register TDR SZM L2ED L2EAL2T L1T L1EA L2T Three bits disables the address breakpoint Program Counter Breakpoint/Mask Registers PBR0-3, PbmrNo inversion Invert data breakpoint comparators Mask Reset 15. PBR0 Field DescriptionsDRc 0x08 PBR0 DRc 0x09 Pbmr Address Breakpoint Registers ABLR, Abhr 17. Pbmr Field DescriptionsAbhr Ablr Data Breakpoint and Mask Registers DBR, Dbmr 19. Abhr Field Description21. Dbmr Field Descriptions Background Debug Mode BDM 22. Access Size and Operand Data LocationAddress1 Access Size Operand Location Resulting Set of Possible Trigger Combinations CPU Halt 23. CPU Halt SourcesHalt Source Halt Timing Description Cpucrard = Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details 15. BDC Host-to-Target Serial Bit Timing Freescale Semiconductor 385 16. BDC Target-to-Host Serial Bit Timing Logic BDM Command Set Descriptions Freescale Semiconductor 387 Miscellaneous Commands Memory CommandsCore Register Commands PST Trace Buffer Read Commands 24. BDM Command Code Field Descriptions CRGCRG CRN VBR BDM Command Set Summary 25. BDM Command SummaryAckdisable Ackenable Readcreg ReaddregReadpstb Syncpc Writecreg Disable host/target handshake protocol Always Available Enable host/target handshake protocol Always Available0x03 Freescale Semiconductor 393 Enter active background mode if enabled Non-intrusive 0x32 Host → Target Memory data7-0 Target → 0x36Data7-0 0x3A Memory 0x33 Xcsrsb0x37 0x3B 0x12 Memory data7-0 Target 0x16 Memory Data15-8 Memory data7-00x12 Memory Target → Host 0x16 Memory No operation Non-intrusive Read CPU control register Active Background Read debug control register Non-intrusive 0xA0+CRN Host → Target Dreg data0x30 Address23-0 Target Memory data7-0 Target → Host 0x31 0x350x39 0x50+CRN Host → Target Pstb data Read general-purpose CPU register Active Background Read Xcsr Status Byte Always AvailableRead CSR2 Status Byte Always Available Read CSR3 Status Byte Always Available Synchronize PC to PST/DDATA Signals Non-intrusive Write CPU control register Active Background0xC0+CRN Creg data Freescale Semiconductor 401 Write debug control register Non-intrusive 0x80+CRN Dreg data0x10 Address23-0 Memory Data7-0 Host → target Write general-purpose CPU register Active Background Serial Interface Hardware Handshake Protocol Write Xcsr Status Byte Always AvailableWrite CSR2 Status Byte Always Available Write CSR3 Status Byte Always Available 19. Target Acknowledge Pulse ACK Freescale Semiconductor 405 Hardware Handshake Abort Procedure 20. Handshake Protocol at Command Level 21signal timing is not drawn to scale Freescale Semiconductor 407 21. ACK Abort Procedure at the Command Level Real-Time Debug Support Real-Time Trace SupportFreescale Semiconductor 409 Enter user mode 26. Processor Status EncodingsPST40 Definition Instructions, generate different encodings Begin Execution of Taken Branch PST = 0x08-0x0BFreescale Semiconductor 411 23. Example JMP Instruction Output in Pstb PST Values Description PST Trace Buffer Pstb 18.4.3.3 PST/DDATA ExamplePstbpst Pstbddata Processor Status, Debug Data Definition 27. PST/DDATA Specification for User-Mode Instructions Instruction Operand SyntaxPST/DDATA Freescale Semiconductor 415 416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set GND Reset Freescale-Recommended BDM PinoutNo Connect Freescale Semiconductor 419 420 Freescale Semiconductor Appendix a Revision History Changes between Rev and RevMCF51QE128RM Rev to Rev Changes Chapter Description Revision History Page How to Reach Us