Freescale Semiconductor MCF51QE128RM 6.7.7 Port G Registers

MCF51QE128 MCU Series Reference Manual, Rev. 3
134 Freescale Semiconductor
Get the latest version from freescale.com
Chapter 6 Parallel Input/Output Control
6.7.7 Port G Registers
Port G is controlled by the registers listed below.
6.7.7.1 Port G Data Register (PTGD)
6.7.7.2 Port G Data Direction Register (PTGDD)
Table 6-36. PTFDS Register Field Descriptions
Field Description
7–0
PTFDSn
Output Drive Strength Selection for Port F Bits. Each of these control bits selects between low and high output
drive for the associated PTF pin. For port F pins configured as inputs, these bits have no effect.
0 Low output drive strength selected for port F bit n.
1 High output drive strength selected for port F bit n.
76543210
R
PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
W
Reset:00000000
Figure 6-40. Port G Data Register (PTGD)
Table 6-37. PTGD Register Field Descriptions
Field Description
7–0
PTGDn
Port G Data Register Bits. For port G pins configured as inputs, reads return the logic level on the pin. For port
G pins configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins configured as outputs, the logic level is driven out
the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pull-ups disabled.
76543210
R
PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
W
Reset:00000000
Figure 6-41. Port G Data Direction Register (PTGDD)
Table 6-38. PTGDD Register Field Descriptions
Field Description
7–0
PTGDDn
Data Direction for Port G Bits. These read/write bits control the direction of port G pins and what is read for PTGD
reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.