Freescale Semiconductor MCF51QE128RM manual BDC Target-to-Host Serial Bit Timing Logic

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

BDC CLOCK (TARGET MCU)

HOST DRIVE TO BKGD PIN

HIGH-IMPEDANCE

TARGET MCU
SPEEDUP PULSE	HIGH-IMPEDANCE
HIGH-IMPEDANCE

PERCEIVED START

OF BIT TIME

	R-C RISE
BKGD PIN
			10 CYCLES	EARLIEST START
		10 CYCLES			OF NEXT BIT

HOST SAMPLES BKGD PIN

Figure 18-16. BDC Target-to-Host Serial Bit Timing (Logic 1)

Figure 18-17shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time, but the target MCU finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles after starting the bit time.

MCF51QE128 MCU Series Reference Manual, Rev. 3

386 Freescale Semiconductor

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