Freescale Semiconductor MCF51QE128RM - page 386

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
MCF51QE128 MCU Series Reference Manual, Rev. 3
386 Freescale Semiconductor
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Figure 18-16. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 18-17 shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous
to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the start
of the bit time as perceived by the target MCU. The host initiates the bit time, but the target MCU finishes
it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock
cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles
after starting the bit time.
HOST SAMPLES BKGD PIN
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TAR GET MC U
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE HIGH-IMPEDANCE
BKGD PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT