SPI Clock Formats Cpha = | Freescale Semiconductor MCF51QE128RM

	Bit Time #	1	2
	(REFERENCE)	1	2
	(REFERENCE)
	SPSCK
	(CPOL = 0)
	SPSCK
	(CPOL = 1)
	SAMPLE IN
	(MISO OR MOSI)
	MOSI
	(MASTER OUT)
	msb FIRST	BIT 7	BIT 6
	lsb FIRST	BIT 0	BIT 1
	MISO
	(SLAVE OUT)
	SS OUT
	(MASTER)
	SS IN
	(SLAVE)

...	6	7	8
...	BIT 2	BIT 1	BIT 0
...	BIT 5	BIT 6	BIT 7

Figure 16-10. SPI Clock Formats (CPHA = 1)

When CPHA is set, the slave begins to drive its MISO output when SS asserts, but the data is not defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge, the SPI shifter shifts one bit position that shifts in the bit value that was sampled, and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave, respectively. When CHPA is set, the slave’s SS input is not required to negate between transfers.

Figure 16-11shows the clock formats when CPHA is cleared. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN asserts), and bit 8 ends at the last SPSCK edge. The msb first and lsb first lines show the order of SPI data bits depending on the setting of SPIxC1[LSBFE]. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE are set). The master SS output asserts at the start of the first bit time of the transfer and negates one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor

327

Get the latest version from freescale.com

Image 327

Freescale Semiconductor MCF51QE128RM manual SPI Clock Formats Cpha =, Freescale Semiconductor 327

Contents

MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Freescale Semiconductor Chapter Resets, Interrupts, and General System Control Title Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Chapter Inter-Integrated Circuit S08IICV2 Section Number Title Real-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History Devices in the MCF51QE128/64/32 Series MCF51QE128 Series Features by MCU and PackageFeature MCF51QE128 Chapter Device Overview Xosc MCU Block Diagram MCF51QE128/64/32 Block Diagram Module Versions V1 ColdFire CoreSystem Clocks Internal Clock Source ICS Module System Clock Distribution Simplified ICS Block Diagram Icsirclk FLL Engaged External FEE FLL Bypassed Internal Low-Power FbilpICS Modes of Operation FLL Engaged Internal FEI Stop Stop FLL Bypassed External Low-Power Fbelp Get the latest version from freescale.com Get the latest version from freescale.com Device Pin Assignment Chapter Pins and Connections Pin Lqfp Pins in bold are added from the next smaller package Recommended System Connections Basic System Connections Power Reset and RstoOscillator Background / Mode Select BKGD/MS General-Purpose I/O and Peripheral Ports ADC Reference Pins VREFH, Vrefl Number Port Pin Alt Pin Assignment by Package and Pin Sharing PriorityPin Priority Port Pin Alt Number Get the latest version from freescale.com Features Chapter Modes of OperationIntroduction Overview MCF51QE128/64/32 Power Modes Conceptual Drawing PMC CPU / Power Mode Selections Run Stop2 LPrun Mode Regulator StateStop3 Full On Transition # From Trigger Triggers for Transitions Shown in Figure Secure Mode Debug Mode Run Modes Run ModeLow-Power Run Mode LPrun BDM in Low-Power Run Mode Wait Modes Wait ModeLow-Power Wait Mode LPwait BDM in Low-Power Wait Mode Stop2 Mode Stop3 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop ModeLow-Range Oscillator Considerations for Stop2 CF1CORE On-Chip Peripheral Modules in Stop and Low-Power ModesLow-Power Mode Behavior Abbreviations used in Table IRQ BDCCOP ICS Get the latest version from freescale.com Get the latest version from freescale.com RAM Chapter MemoryMCF51QE128/64/32 Memory Map Kbytes Long Byte CPU Access Type Allowed by RegionRegister Addresses and Bit Assignments Read Write Base Address Region Byte ColdFire Memory Organization Direct-Page Register Summary Sheet 1 Register Address Name Direct-Page Register Summary Sheet 2 Direct-Page Register Summary Sheet 3 High-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 4 High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 0x0 0x1 0x2 0x3 Flash Module Reserved Memory LocationsHigh-Page Register Summary Sheet 5 Reserved Flash Memory Addresses Nvprot 0x0 0x1 0x2 0x3 0x000004080x0000040C Reserved Flash Memory Addresses Register V1 ColdFire Interrupt Controller Memory Map ColdFire Rapid Gpio Memory MapColdFire Interrupt Controller Memory Map V1 ColdFire Rapid Gpio Memory Map Intccfrc RAMFlash Intcsfrc Features Lov-Voltage Programming Sequence ExampleAddresses Desired Value Values Programmed Fcdiv Field Descriptions Register DescriptionsFlash Clock Divider Register Fcdiv Flash Options Register Fopt and Nvopt 10. Fopt Field Descriptions Flash Configuration Register Fcnfg 13. Flash Protection Address Range Flash Protection Register Fprot and Nvprot11. Fcnfg Field Descriptions 12. Fprot Field Descriptions 0x42 0x00-0x3F0x40 0x41 0x00000-0x1EFFF W1c Command buffers are fullFlash Status Register Fstat Fcbef Fccf Fpviol Faccerr Fblank 15. Fcmd Field Descriptions Flash Command OperationsFlash Command Register Fcmd Function Description 200 195 ⎟ 200 = 3% Writing the Fcdiv Register ALL Program and Erase Command Write SequenceCommands Impossible Start Fcmd NVM Flash CommandsErase Verify Command 16. Flash Command Description Program Command 11. Example Program Command Flow Burst Program Command Programming Sector Erase CommandCommand Buffer Empty Sequential 13. Example Sector Erase Command Flow 14. Example Mass Erase Command Flow Mass Erase Command Illegal Flash Operations Flash Access Violations Flash Protection Violations Wait ModeBackground Debug Mode Operating Modes Security Unsecuring the MCU using Backdoor Key Access Program and Erase Times ResetsFlash Reset Sequence Reset While Flash Command Active Security Device is unsecure SyncSet PRDIV8 and clock divider fields in CSR3 Stop Microcontroller Reset Chapter Resets, Interrupts, and General System Control Copclks Copt COP Configuration OptionsComputer Operating Properly COP Watchdog Control Bits Clock Source COP Overflow Count Interrupts and Exceptions Illegal Operation ResetIllegal Address Reset Pin Configuration Options External Interrupt Initialization Power-On Reset OperationLow-Voltage Detect LVD System Edge and Level Sensitivity Low-Voltage Warning LVW Interrupt Operation LVD Reset OperationPeripheral Clock Gating LVD Interrupt Operation Irqpdd Interrupt Pin Request Status and Control Register IrqscIrqsc Register Field Descriptions Irqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack POR System Reset Status Register SRS POR LVR System Options Register 1 SOPT1 SOPT1 Register Field Descriptions System Options Register 2 SOPT2 IIC1PS SDA1 SCL1 System Device Identification Register SDIDH, SdidlSOPT2 Register Field Descriptions SPI1PS SPSCLK1 MOSI1 MISO1 SS1 Sdidh Register Field Descriptions Sdidl Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack LPR Lprs Lpwui Ppde Ppdc Ppdack SPMSC1 Register Field Descriptions SPMSC2 Register Field Descriptions Lvdvlvwv 11. LVD and LVW Trip Point Typical Values1Lvwf Lvdv Lvwv Lvwie Lvwf TPM3 System Clock Gating Control 1 Register SCGC1System Clock Gating Control 2 Register SCGC2 12. SCGC1 Register Field Descriptions 13. SCGC2 Register Field Descriptions RTC SPI2 SPI1FLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Chapter Parallel Input/Output Control Port Data and Data DirectionFreescale Semiconductor 113 Data Direction Control Port Data Register Port Read Port Internal Pull-up EnablePort Slew Rate Enable Pull-up, Slew Rate, and Drive Strength Port Data Set, Clear and Toggle Data Registers Port Drive Strength SelectFreescale Semiconductor 115 Port Data Clear Registers V1 ColdFire Rapid Gpio FunctionalityKeyboard Interrupts Port Data Set Registers Freescale Semiconductor 117 Edge Only SensitivityEdge and Level Sensitivity Pull-up/Pull-down Resistors Port a Registers Pin Behavior in Stop ModesParallel I/O, Keyboard Interrupt, and Pin Control Registers Keyboard Interrupt Initialization PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0 Port a Pull Enable Register PtapePort a Data Register Ptad Port a Data Direction Register Ptadd PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 Port a Slew Rate Enable Register PtasePort a Drive Strength Selection Register Ptads PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 Ptads Register Field Descriptions Port B RegistersPort B Data Register Ptbd Port B Data Direction Register Ptbdd Ptbpe Register Field Descriptions Port B Pull Enable Register PtbpePort B Slew Rate Enable Register Ptbse Ptbdd Register Field Descriptions 10. Ptbds Register Field Descriptions Port C RegistersPort B Drive Strength Selection Register Ptbds Port C Data Register Ptcd 12. Ptcdd Register Field Descriptions Port C Data Direction Register PtcddPort C Data Set Register Ptcset Port C Data Clear Register Ptcclr 16. Ptcpe Register Field Descriptions Port C Pull Enable Register PtcpePort C Toggle Register Ptctog 14. Ptcclr Register Field Descriptions Port D Data Register Ptdd Port C Slew Rate Enable Register PtcsePort D Registers Port C Drive Strength Selection Register Ptcds 20. Ptddd Register Field Descriptions Port D Pull Enable Register PtdpePort D Data Direction Register Ptddd 19. Ptdd Register Field Descriptions Port E Data Register Pted Port D Slew Rate Enable Register PtdsePort E Registers Port D Drive Strength Selection Register Ptdds 25. Ptedd Register Field Descriptions Port E Data Direction Register PteddPort E Data Set Register Pteset 24. Pted Register Field Descriptions PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 Port E Pull Enable Register PtepePort E Data Clear Register Pteclr Port E Toggle Register Ptetog 30. Ptese Register Field Descriptions Port E Slew Rate Enable Register PtesePort E Drive Strength Selection Register Pteds 29. Ptepe Register Field Descriptions Port F Data Direction Register Ptfdd Port F Pull Enable Register PtfpePort F Registers Port F Data Register Ptfd 35. Ptfse Register Field Descriptions Port F Slew Rate Enable Register PtfsePort F Drive Strength Selection Register Ptfds 34. Ptfpe Register Field Descriptions 36. Ptfds Register Field Descriptions Port G RegistersPort G Data Register Ptgd Port G Data Direction Register Ptgdd 39. Ptgpe Register Field Descriptions Port G Pull Enable Register PtgpePort G Slew Rate Enable Register Ptgse Port G Drive Strength Selection Register Ptgds 41. Ptgds Register Field Descriptions Port H RegistersPort H Data Register Pthd Port H Data Direction Register Pthdd 44. Pthpe Register Field Descriptions Port H Pull Enable Register PthpePort H Slew Rate Enable Register Pthse Port H Drive Strength Selection Register Pthds Port J Registers Port J Data Register PtjdPort J Data Direction Register Ptjdd 49. Ptjpe Register Field Descriptions Port J Pull Enable Register PtjpePort J Slew Rate Enable Register Ptjse Port J Drive Strength Selection Register Ptjds 52. KBI1 Pin Mapping Keyboard Interrupt 1 KBI1 Registers10.1 KBI1 Interrupt Status and Control Register KBI1SC 51. Ptjds Register Field Descriptions Keyboard Interrupt 1 KBI2 Registers 10.2 KBI1 Interrupt Pin Select Register KBI1PE10.3 KBI1 Interrupt Edge Select Register KBI1ES 58. KBI2PE Register Field Descriptions 11.1 KBI2 Interrupt Status and Control Register KBI2SC11.2 KBI2 Interrupt Pin Select Register KBI2PE 57. KBI2SC Register Field Descriptions 11.3 KBI2 Interrupt Edge Select Register KBI2ES 59. KBI2ES Register Field DescriptionsFreescale Semiconductor 143 144 Freescale Semiconductor Overview Chapter ColdFire Core Memory Map/Register Description ColdFire Core Programming Model Supervisor/User Access RegistersSupervisor Access Only Registers Data Registers D0-D7 Address Registers A0-A6 Supervisor/User Stack Pointers A7 and OTHERA7Data Freescale Semiconductor 149 Condition Code Register CCR Program Counter PC Vector Base Register VBRCCR Field Descriptions CPU Configuration Register Cpucr Status Register SR SR Field DescriptionsBWD Instruction Description Functional DescriptionInstruction Set Architecture Isac Instruction Enhancements over Revision Isaa Exception Processing Overview Exception Vector Assignments Vector StackedAssignment Numbers Offset Hex Counter SSP → Exception Stack Frame DefinitionAssignment Numbers Offset Hex Counter FS30 Definition Fault Status Encodings2.2 S08 and ColdFire Exception Processing Comparison Format Field Encodings Exception Processing Comparison Attribute S08 V1 ColdFireRTI RTE Freescale Semiconductor 159 Access Error ExceptionAddress Error Exception Processor Exceptions OpwordLine Instruction Class Illegal Instruction Exception10. ColdFire Opword Line Definition Line OpMode Effective Address Privilege Violation Trace ExceptionFreescale Semiconductor 161 Debug Interrupt RTE and Format Error ExceptionUnimplemented Line-A Opcode Unimplemented Line-F Opcode Interrupt Exception Fault-on-Fault HaltTrap Instruction Exception Unsupported Instruction Exception VER REV Reset ExceptionAccess User read-only BDM read-only BDM Load 0x60 D0 Store 0x40 D0 11. D0 Hardware Configuration Info Field Description 12. D1 Hardware Configuration Information Field Description FlashszSramsz Address10 Size Bus Additional Operations CR/W Instruction Execution TimingTiming Assumptions 13. Misaligned Operand References Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl Move Instruction Execution Times14. Move Byte and Word Execution Times 15. Move Long Execution Times Standard One Operand Instruction Execution Times 16. One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx 17. Two Operand Instruction Execution Times Standard Two Operand Instruction Execution Times Miscellaneous Instruction Execution Times 18. Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Branch Instruction Execution Times 19. General Branch Instruction Execution Times20. Bcc Instruction Execution Times Chapter Interrupt Controller CF1INTC AttributeHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x180 Next 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x1440x148 Next ACMPx 0x14C 0x150 Next SCI2rx 0x154 SCI2tx 0x158 Interrupt Source Number To V1 ColdFire coreFreescale Semiconductor 177 External Signal Description Memory Map and Register DefinitionModes of Operation Memory Map Intc Force Interrupt Register IntcfrcCF1INTC Memory Map Intcfrc Field Descriptions Intc Wake-up Control Register Intcwcr INTCPL6P7,6 Field DescriptionsFreescale Semiconductor 181 Intc Set Interrupt Force Register Intcsfrc Intcwcr Field DescriptionsENB Offset CF1INTCBASE + 0x1F Intccfrc Intc Clear Interrupt Force Register IntccfrcIntcsfrc Field Descriptions Intccfrc Field Descriptions Vecn Swiack Intc Software and Level-nIACK Registers n = 1,2,3,...,7 Priority within Level Midpoint Interrupt Request Level and Priority AssignmentsINTCSWIACK, INTCLVLnIACK Field Descriptions 10. Legend for Table 12. V1 ColdFire Interrupt Assignments TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovflTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Initialization Information Application InformationEmulation of the HCS08’s 1-Level IRQ Handling Using INTCPL6P7,6 Registers More on Software IACKsFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Freescale Semiconductor 193 Chapter Rapid Gpio Rgpio V1 ColdFire Core Freescale Semiconductor 195 RAM Rgpio IFPCore OEP Dsoc RGPIODATA150 RgpioModule Pin Muxing + Pad Logic On-platform Bus Detailed Signal Descriptions Rgpio Module External I/O SignalsRgpio Detailed Signal Descriptions Memory Map/Register Definition Rgpio Write Memory MapRgpio Read Memory Map DIR Rgpio Data Direction RgpiodirRgpio Data Rgpiodata Rgpiodir Field Descriptions Rgpio Clear Data Rgpioclr Rgpio Pin Enable Rgpioenb Rgpioset Field Descriptions Rgpio Set Data RgpiosetRgpio Toggle Data Rgpiotog Rgpioclr Field Descriptions Field Description 15-0 Rgpio Toggle Data Application 1 Simple Square-Wave Generation10. Rgpiotog Field Descriptions TOG 11. Square-Wave Output Performance Freescale Semiconductor 205 12. Emulated SPI Performance using Gpio OutputsSPI Speed @ Relative CPU f = 50 MHz 29x 206 Freescale Semiconductor Acmp Clock Gating Acmp Configuration InformationACMP/TPM Configuration Information Chapter Analog Comparator 3V ACMPVLPV1 Interrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Stop2 Mode Operation Block DiagramWait Mode Operation Stop3 Mode Operation Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF Register DefinitionStatus and Control Register ACMPxSC Acbgs Acpe Acmod InterruptsACMPxSC Field Descriptions Acme 214 Freescale Semiconductor Chapter Analog-to-Digital Converter S08ADC12V1 ADC Clock GatingFreescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 ADC Channel Assignment Module ConfigurationsChannel Assignments Alternate Clock Hardware Trigger Temperature Sensor Freescale Semiconductor 219 2provides a block diagram of the ADC module Signal Properties Name FunctionAD27-AD0 Voltage Reference Low Vrefl Analog Power VddadAnalog Ground Vssad Voltage Reference High Vrefh Coco Input Channel SelectInput Select Adact Status and Control Register 2 ADCSC2Data Result High Register Adcrh ADCSC2 Register Field Descriptions ADCV11 ADCV10 ADCV9 ADCV8 Data Result Low Register AdcrlCompare Value High Register Adccvh ADR10 ADR9 ADR8 Adlpc Configuration Register AdccfgCompare Value Low Register Adccvl Adccfg Register Field Descriptions Input Clock Select Pin Control 1 Register APCTL1Clock Divide Select Conversion Modes Pin Control 2 Register APCTL2 10. APCTL1 Register Field DescriptionsADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 ADPC23 Pin Control 3 Register APCTL311. APCTL2 Register Field Descriptions ADPC15 ADPC16 12. APCTL3 Register Field DescriptionsADPC21 ADPC20 Conversion Control Clock Select and Divide ControlInput Select and Pin Control Hardware Trigger Freescale Semiconductor 231 Initiating ConversionsCompleting Conversions Aborting Conversions Adiclk Adlsmp Power ControlSample Time and Total Conversion Time 13. Total Conversion Time vs. Control Conditions Automatic Compare Function MCU Wait Mode Operation Stop3 Mode With Adack Enabled MCU Stop3 Mode OperationMCU Stop2 Mode Operation Stop3 Mode With Adack Disabled Freescale Semiconductor 235 ADC Module Initialization ExampleInitialization Sequence Pseudo-Code Example Yes Read Adcrh Then Adcrl To Clear Coco Bit Continue External Pins and RoutingReset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No COCO=1? Freescale Semiconductor 237 Analog Supply PinsAnalog Reference Pins Analog Input Pins Noise-Induced Errors Sources of ErrorSampling Error Pin Leakage Error Freescale Semiconductor 239 Code Width and Quantization ErrorLinearity Errors Lsb = Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor Freescale Semiconductor 243 Stop2 Mode ConsiderationsChapter Internal Clock Source S08ICSV3 External Oscillator Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor Freescale Semiconductor 247 HGO, RANGE, EREFS, ERCLKEN, Erefsten 2is the ICS block diagram Rdiv Irefs FLL Bypassed Internal Low Power FbilpFLL Bypassed External Low Power Fbelp ICS Register Summary Reference Divide Factor ICS Control Register 1 ICSC1ICSC1 Field Descriptions Clks Rdiv Irefs Irclken Irefsten Bdiv Range HGO Erefs Erclken Erefsten ICS Control Register 2 ICSC2ICS Trim Register Icstrm ICSC2 Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRS ICS Status and Control IcsscIcstrm Field Descriptions Icssc Field Descriptions 1024 32 40 MHz Reference range FLL factor DCO range512 16 20 MHz 608 19.92 MHz IREFS=0 CLKS=10 Operational ModesFLL Engaged Internal FEI IREFS=1 CLKS=00 IREFS=0 FLL Bypassed External FBE FLL Bypassed Internal Low Power FbilpFLL Engaged External FEE FLL Bypassed Internal FBI Stop Mode SwitchingFLL Bypassed External Low Power Fbelp Bus Frequency Divider External Reference Clock Low Power Bit UsageDCO Maximum Frequency with 32.768 kHz Oscillator Internal Reference Clock Local Clock Fixed Frequency Clock SOPT2IIC1PS Module ConfigurationChapter Inter-Integrated Circuit S08IICV2 IIC1 Position Options MCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SCL Serial Clock Line SDA Serial Data LineFreescale Semiconductor 263 = Unimplemented or Reserved IIC Address Register IicaIIC Frequency Divider Register Iicf Iica Field Descriptions Mult ICR SDA Iicf Field DescriptionsHold Time Values for 8 MHz Bus Speed Hold Times μs ICR SCL IIC Divider and Hold Values IICC1 Field Descriptions IIC Control Register IICC1 IIC Status Register Iics Iics Field DescriptionsTCF Freescale Semiconductor 269 IIC Data I/O Register IicdIIC Control Register 2 IICC2 Iicd Field Descriptions IIC Protocol IICC2 Field DescriptionsGcaen Start Signal Slave Address TransmissionFreescale Semiconductor 271 Data Transfer Stop SignalRepeated Start Signal Arbitration Procedure Freescale Semiconductor 273 Clock SynchronizationHandshaking Clock Stretching 13.4.2 10-bit Address Master-Transmitter Addresses a Slave-ReceiverMaster-Receiver Addresses a Slave-Transmitter Address Detect Interrupt ResetsGeneral Call Address Byte Transfer Interrupt 276 Freescale Semiconductor Module Use Initialization/Application InformationModule Initialization Slave Module Initialization Master 12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor RTC Modes of Operation Chapter Real-Time Counter S08RTCV1ADC Hardware Trigger RTC Clock Sources Interrupt Vector Freescale Semiconductor 283 MCF51QE128 Block Diagram Highlighting RTC Block and Pins Active Background Mode Irclk RTC Register SummaryLPO Erclk Rtif RTC Status and Control Register RtcscRtcsc Field Descriptions RTC Prescaler Divide-by values Rtcmod Field Descriptions RTC Counter Register RtccntRTC Modulo Register Rtcmod Rtccnt Field Descriptions KHz Internal Clock MHz External Clock Rtclks = RTC Operation ExamplePrescaler Period Rtcps Freescale Semiconductor 289 Internal 1-kHz Clock Source RTC Clock Rtcps =Rtccnt Rtif 0x52 0x53 0x54 0x55 0x00 0x01 290 Freescale Semiconductor Chapter Serial Communications Interface S08SCIV4 SCI Clock GatingFreescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI Freescale Semiconductor 297 SCI Receiver Block Diagram SCI Baud Rate Registers SCIxBDH, SCIxBDL SCIxBDH Field DescriptionsLbkdie Loops SCI Control Register 1 SCIxC1SCIxBDL Field Descriptions Loops Sciswai Rsrc Wake ILT SCI Control Register 2 SCIxC2 SCIxC2 Field DescriptionsTIE Tdre Rdrf Idle SCI Status Register 1 SCIxS1 SCIxD Framing errorNo parity error Parity error RXINV1 SCI Status Register 2 SCIxS2SCIxS2 Field Descriptions Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF TXINV1 SCI Control Register 3 SCIxC3SCIxC3 Field Descriptions Txdir SCI Data Register SCIxD Baud Rate GenerationFreescale Semiconductor 305 Send Break and Queued Idle Transmitter Functional Description BRK13 Receiver Functional DescriptionData Sampling Technique Break Character Length Idle-Line Wakeup Receiver Wakeup Operation Freescale Semiconductor 309 Interrupts and Status Flags 15.3.5.1 8- and 9-Bit Data Modes Stop Mode OperationLoop Mode Additional SCI Functions Freescale Semiconductor 311 Single-Wire Operation 312 Freescale Semiconductor Chapter Serial Peripheral Interface S08SPIV3 SPI Clock GatingFreescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor Block Diagrams SPI System Block DiagramFreescale Semiconductor 317 SPI Module Block Diagram Freescale Semiconductor 319 SPI Baud Rate Generation SS Slave Select Spsck SPI Serial ClockMosi Master Data Out, Slave Data Miso Master Data In, Slave Data Out SPIxC1 Field Descriptions Modes of OperationSPI in Stop Modes SPI Control Register 1 SPIxC1 Modfen Ssoe Master Mode Slave ModeSPI Control Register 2 SPIxC2 SS Pin Function Modfen Bidiroe Spiswai SPI Stop in Wait ModeSPI Baud Rate Register SPIxBR SPIxC2 Register Field Descriptions SPR SPI Status Register SPIxSSPIxBR Register Field Descriptions Sppr SPI Data Register SPIxD SPI Clock Formats Freescale Semiconductor 327 10. SPI Clock Formats Cpha = 11. SPI Clock Formats Cpha = SPI Interrupts Freescale Semiconductor 329 Mode Fault Detection 330 Freescale Semiconductor Chapter Timer/Pulse-Width Modulator S08TPMV3 TPM Clock GatingFreescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor Freescale Semiconductor 337 TPM Block Diagram Extclk Signal Description TPMxCHn TPM Channel n I/O Pins Extclk External Clock SourceFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TOF TPM Status and Control Register TPMxSCTPMxSC Field Descriptions TOF Toie Cpwms Clksb Clksa PS2 PS1 Clksbclksa TPM Counter Registers TPMxCNTHTPMxCNTLTPM-Clock-Source Selection Prescale Factor Selection Freescale Semiconductor 343 TPM Counter Modulo Registers TPMxMODHTPMxMODLTPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter TPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter CHnF CHnIE MSnB MSnA ELSnB ELSnA TPM Channel n Status and Control Register TPMxCnSCTPMxMOD158 TPMxMOD70 Cpwms MSnBMSnA ELSnBELSnA Mode ConfigurationTPMxCnSC Field Descriptions Mode, Edge, and Level Selection TPMxCnV70 TPM Channel Value Registers TPMxCnVHTPMxCnVLMode, Edge, and Level Selection TPMxCnV158 Counter Counter Clock SourceFreescale Semiconductor 347 TPM Clock Source Selection Counter Overflow and Modulo Reset Output Compare Mode Channel Mode SelectionManual Counter Reset Input Capture Mode 15. PWM Period and Pulse Width ELSnA=0 Edge-Aligned PWM Mode Freescale Semiconductor 351 Center-Aligned PWM Mode Reset Overview Description of Reset OperationGeneral Interrupt Summary Timer Overflow Interrupt TOF DescriptionInterrupt Local Source Description Enable Description of Interrupt Operation Center-Aligned PWM Case Channel Event Interrupt Description Freescale Semiconductor 355 Chapter Version 1 ColdFire Debug CF1DEBUG Bkgd BDC Version 1 ColdFire Core CF1CoreOEP PST Csrhrl CSR2D1HRL Modes of OperationsDebug Revision Summary Revision BDM? BDM Command TypesCommand Type Flash Core Status Command Set External Signal Descriptions Debug Module Signals DescriptionBDM GO DRc Register Name Width Access Reset Value Section Bits Debug Module Memory MapCPU Configuration/Status Register CSR CSR Field Descriptions Bstat FOF TRG Halt Bkpt HRL BKD IPWTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Extended Configuration/Status Register Xcsr Xcsr Reference SummaryMethod Reference Details CPU State CPU Cstat Halt Stop Eseqc Clksw SEC Erase EnbdmApcsc Apce Xcsr Eseqc W SEC RErase W Syncpc Interval Configuration/Status Register 2 CSR2CSR2 Reference Summary Xcsr CSR2 CSR2 Field Descriptions Pstb Valid Data Locations Oldest to Newest PSTBWA7 Start Condition Stop Condition Configuration/Status Register 3 CSR310. CSR3 Reference Summary Pstbss BDM Address Attribute Register Baar BFC Bfcdiv DIV8BFCDIV8 SZM TTM TMM Address Attribute Trigger Register Aatr SZM Signal of the processor’s local busBDM memory commands Normal processor access Else Reserved Trigger Definition Register TDR L1EA L2EDL2EA L2T L1T L2T Three bits disables the address breakpoint Program Counter Breakpoint/Mask Registers PBR0-3, PbmrNo inversion Invert data breakpoint comparators DRc 0x09 Pbmr Mask Reset15. PBR0 Field Descriptions DRc 0x08 PBR0 Ablr Address Breakpoint Registers ABLR, Abhr17. Pbmr Field Descriptions Abhr Data Breakpoint and Mask Registers DBR, Dbmr 19. Abhr Field Description21. Dbmr Field Descriptions Resulting Set of Possible Trigger Combinations Background Debug Mode BDM22. Access Size and Operand Data Location Address1 Access Size Operand Location Cpucrard = CPU Halt23. CPU Halt Sources Halt Source Halt Timing Description Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details Freescale Semiconductor 385 15. BDC Host-to-Target Serial Bit Timing 16. BDC Target-to-Host Serial Bit Timing Logic Freescale Semiconductor 387 BDM Command Set Descriptions PST Trace Buffer Read Commands Miscellaneous CommandsMemory Commands Core Register Commands VBR 24. BDM Command Code Field DescriptionsCRG CRG CRN Ackenable BDM Command Set Summary25. BDM Command Summary Ackdisable Readcreg ReaddregReadpstb Writecreg Syncpc Freescale Semiconductor 393 Disable host/target handshake protocol Always AvailableEnable host/target handshake protocol Always Available 0x03 0x3A Memory Enter active background mode if enabled Non-intrusive0x32 Host → Target Memory data7-0 Target → 0x36 Data7-0 0x3B 0x33Xcsrsb 0x37 Target → Host 0x16 Memory 0x12 Memory data7-0Target 0x16 Memory Data15-8 Memory data7-0 0x12 Memory Read CPU control register Active Background No operation Non-intrusive Target Memory data7-0 Target → Host Read debug control register Non-intrusive0xA0+CRN Host → Target Dreg data 0x30 Address23-0 0x50+CRN Host → Target Pstb data 0x310x35 0x39 Read CSR3 Status Byte Always Available Read general-purpose CPU register Active BackgroundRead Xcsr Status Byte Always Available Read CSR2 Status Byte Always Available Freescale Semiconductor 401 Synchronize PC to PST/DDATA Signals Non-intrusiveWrite CPU control register Active Background 0xC0+CRN Creg data Host → target Write debug control register Non-intrusive0x80+CRN Dreg data 0x10 Address23-0 Memory Data7-0 Write general-purpose CPU register Active Background Write CSR3 Status Byte Always Available Serial Interface Hardware Handshake ProtocolWrite Xcsr Status Byte Always Available Write CSR2 Status Byte Always Available Freescale Semiconductor 405 19. Target Acknowledge Pulse ACK 20. Handshake Protocol at Command Level Hardware Handshake Abort Procedure Freescale Semiconductor 407 21signal timing is not drawn to scale 21. ACK Abort Procedure at the Command Level Real-Time Debug Support Real-Time Trace SupportFreescale Semiconductor 409 Instructions, generate different encodings Enter user mode26. Processor Status Encodings PST40 Definition Begin Execution of Taken Branch PST = 0x08-0x0BFreescale Semiconductor 411 PST Values Description 23. Example JMP Instruction Output in Pstb Pstbddata PST Trace Buffer Pstb18.4.3.3 PST/DDATA Example Pstbpst Processor Status, Debug Data Definition Freescale Semiconductor 415 27. PST/DDATA Specification for User-Mode InstructionsInstruction Operand Syntax PST/DDATA 416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set Freescale Semiconductor 419 GND ResetFreescale-Recommended BDM Pinout No Connect 420 Freescale Semiconductor Chapter Description Appendix a Revision HistoryChanges between Rev and Rev MCF51QE128RM Rev to Rev Changes Revision History Page How to Reach Us