Freescale Semiconductor MCF51QE128RM manual Edge Only Sensitivity, Edge and Level Sensitivity

Chapter 6 Parallel Input/Output Control

			1
KBIxP0			0S
				KBIPE0
	KBEDG0
		1
KBIxPn
			0S
				KBIPEn
	KBEDGn

VDD

DCLRQ

CK

KBIMOD

	KBACK		BUSCLK
	RESET				KBF
			SYNCHRONIZER
KEYBOARD		STOP	STOP BYPASS			KBI
INTERRUPT FF						INTERRUPT
						REQUEST
				KBIE

Figure 6-3. Port Interrupt Block Diagram

Writing to the KBIPEn bits in the keyboard x interrupt pin enable register (KBIxPE) independently enables or disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on KBIxSC[KBIMOD]. Edge sensitivity can be software programmed to be falling or rising; the level can be low or high. The polarity of the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIxES).

Synchronous logic detects edges. Prior to detecting an edge, enabled port inputs must be at the deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle.

6.5.1Edge Only Sensitivity

A valid edge on an enabled port pin sets KBIxSC[KBF]. If the KBIxSC[KBIE] bit is set, an interrupt request is generated to the CPU. Clearing of KBF is accomplished by writing a 1 to KBIxSC[KBACK].

6.5.2Edge and Level Sensitivity

A valid edge or level on an enabled port pin sets KBIxSC[KBF]. If KBIxSC[KBIE] is set, an interrupt request is generated to the CPU. Clearing of KBF is accomplished by writing a 1 to KBIxSC[KBACK], provided all enabled port inputs are at their deasserted levels. KBF remains set if any enabled port pin is asserted while attempting to clear by writing a 1 to KBACK.

6.5.3Pull-up/Pull-down Resistors

The keyboard interrupt pins can be configured to use an internal pull-up/pull-down resistor using the associated I/O port pull-up enable register. If an internal resistor is enabled, the KBIxES register selects whether the resistor is a pull-up (KBEDGn = 0) or a pull-down (KBEDGn = 1).

MCF51QE128 MCU Series Reference Manual, Rev. 3

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