Freescale Semiconductor MCF51QE128RM manual Chapter ColdFire Core, Overview

Chapter 7

ColdFire Core

7.1Introduction

This section describes the organization of the Version 1 (V1) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_C definition in the ColdFire Family Programmer’s Reference Manual.

7.1.1Overview

As with all ColdFire cores, the V1 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer.

	IAG	Instruction
		Address
		Generation
	IC	Instruction
Instruction		Fetch Cycle
Fetch
Pipeline
	IB	FIFO
		Instruction Buffer
Operand	DSOC	Decode & Select,
		Operand Fetch
Execution
Pipeline		Address
	AGEX	Generation,
		Execute

Figure 7-1. V1 ColdFire Core Pipelines

Address [23:0]

Read Data[31:0]

Write Data[31:0]

The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the

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