Freescale Semiconductor MCF51QE128RM guide

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
			# pst	= 1c, 1c, 05, 0d
			# ddata	= 2a, 23, 28, 20
			#		trg_addr = 083a << 1
	_isr:		#		trg_addr = 1074
01074: 46fc 2700	_isr:	&0x2700,%sr	# pst	=	01
01074: 46fc 2700	mov.w	&0x2700,%sr	# pst	=	01
01078: 2f08	mov.l	%a0,-(%sp)	# pst	=	01
0107a: 2f00	mov.l	%d0,-(%sp)	# pst	=	01
0107c: 302f 0008	mov.w	(8,%sp),%d0	# pst	=	01
01080: e488	lsr.l	&2,%d0	# pst	=	01
01082: 0280 0000 00ff	andi.l	&0xff,%d0	# pst	=	01
01088: 207c 0080 1400	mov.l	&int_count,%a0	# pst	=	01
0108e: 52b0 0c00	addq.l	&1,(0,%a0,%d0.l*4)	# pst	=	01
01092: 11c0 a021	mov.b	%d0,IGCR0+1.w	# pst	=	01, 08
			# ddata	= 30, 30
01096: 1038 a020	mov.b	IGCR0.w,%d0	#		wdata.b = 0x00
01096: 1038 a020	mov.b	IGCR0.w,%d0	# pst	= 01, 08
			# ddata	= 28, 21
0109a: 4e71	nop		#	=	rdata.b = 0x18
0109a: 4e71	nop	SWIACK.w,%d0	# pst	=	01
0109c: 71b8 ffe0	mvz.b	SWIACK.w,%d0	# pst	=	01, 08
			# ddata	= 20, 20
010a0: 0c80 0000 0041	cmpi.l	%d0,&0x41	#	=	rdata.b = 0x00
010a0: 0c80 0000 0041	cmpi.l	%d0,&0x41	# pst	=	01	(taken branch)
010a6: 6f08	ble.b	_isr_exit	# pst	=	05	(taken branch)
010b0: 201f	mov.l	(%sp)+,%d0	# pst	=	01
010b2: 205f	mov.l	(%sp)+,%a0	# pst	=	01
010b4: 4e73	rte		# pst	=	07, 03, 05, 0d
			# ddata	=	29, 21, 2a, 22
			#trg_addr		= 2a19 << 1
			#trg_addr		= 5432

As the PSTs are compressed, the resulting stream of 6-bit hexadecimal entries is loaded into consecutive locations in the PST trace buffer:

PSTB[*]= 1c, 1c, 05, 0d,	// interrupt exception			1074
2a, 23, 28, 20,	// branch target addr =			1074
19, 08, 30, 30,	// 9	sequential insts,		write byte
01, 08, 28, 21,	// 1	sequential inst,		read byte
12, 08, 20, 20,	// 2	sequential insts,	2	read byte
01, 05, 12,	// 1	+ taken_branch +	2	sequential
07, 03, 05, 0d,	// rte, entry into user			mode
29, 21, 2a, 22	// branch target addr		=	5432

Architectural studies on the compression algorithm determined an appropriate size for the PST trace buffer. Using a suite of ten MCU benchmarks, a 64-entry PSTB was found to capture an average window of time of 520 processor cycles with program trace using 2-byte addresses enabled.

18.4.3.4Processor Status, Debug Data Definition

This section specifies the ColdFire processor and debug module’s generation of the processor status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an instruction is defined as follows:

PST = 0x01, {PST = [0x89B], DDATA = operand}

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual Processor Status, Debug Data Definition

Contents

MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Chapter Resets, Interrupts, and General System Control Freescale Semiconductor Title Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Section Number Title Chapter Inter-Integrated Circuit S08IICV2 Real-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History Chapter Device Overview MCF51QE128 Series Features by MCU and PackageFeature MCF51QE128 Devices in the MCF51QE128/64/32 Series MCU Block Diagram Xosc MCF51QE128/64/32 Block Diagram Internal Clock Source ICS Module V1 ColdFire CoreSystem Clocks Module Versions Simplified ICS Block Diagram System Clock Distribution Icsirclk FLL Engaged Internal FEI FLL Bypassed Internal Low-Power FbilpICS Modes of Operation FLL Engaged External FEE FLL Bypassed External Low-Power Fbelp Stop Stop Get the latest version from freescale.com Get the latest version from freescale.com Chapter Pins and Connections Device Pin Assignment Pins in bold are added from the next smaller package Pin Lqfp Recommended System Connections Basic System Connections Power Reset and RstoOscillator Background / Mode Select BKGD/MS ADC Reference Pins VREFH, Vrefl General-Purpose I/O and Peripheral Ports Priority Pin Assignment by Package and Pin Sharing PriorityPin Number Port Pin Alt Number Port Pin Alt Get the latest version from freescale.com Features Chapter Modes of OperationIntroduction MCF51QE128/64/32 Power Modes Conceptual Drawing Overview CPU / Power Mode Selections PMC Full On Mode Regulator StateStop3 Run Stop2 LPrun Triggers for Transitions Shown in Figure Transition # From Trigger Debug Mode Secure Mode BDM in Low-Power Run Mode Run ModeLow-Power Run Mode LPrun Run Modes BDM in Low-Power Wait Mode Wait ModeLow-Power Wait Mode LPwait Wait Modes Stop2 Mode Stop3 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop ModeLow-Range Oscillator Considerations for Stop2 Abbreviations used in Table On-Chip Peripheral Modules in Stop and Low-Power ModesLow-Power Mode Behavior CF1CORE ICS BDCCOP IRQ Get the latest version from freescale.com Get the latest version from freescale.com Kbytes Chapter MemoryMCF51QE128/64/32 Memory Map RAM Read Write Base Address Region Byte CPU Access Type Allowed by RegionRegister Addresses and Bit Assignments Long Byte ColdFire Memory Organization Direct-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 2 Register Address Name Direct-Page Register Summary Sheet 3 Direct-Page Register Summary Sheet 4 High-Page Register Summary Sheet 1 High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 Reserved Flash Memory Addresses Flash Module Reserved Memory LocationsHigh-Page Register Summary Sheet 5 0x0 0x1 0x2 0x3 Reserved Flash Memory Addresses Register 0x0 0x1 0x2 0x3 0x000004080x0000040C Nvprot V1 ColdFire Rapid Gpio Memory Map ColdFire Rapid Gpio Memory MapColdFire Interrupt Controller Memory Map V1 ColdFire Interrupt Controller Memory Map Intcsfrc RAMFlash Intccfrc Features Lov-Voltage Programming Sequence ExampleAddresses Desired Value Values Programmed Flash Options Register Fopt and Nvopt Register DescriptionsFlash Clock Divider Register Fcdiv Fcdiv Field Descriptions Flash Configuration Register Fcnfg 10. Fopt Field Descriptions 12. Fprot Field Descriptions Flash Protection Register Fprot and Nvprot11. Fcnfg Field Descriptions 13. Flash Protection Address Range 0x41 0x00000-0x1EFFF 0x00-0x3F0x40 0x42 Fcbef Fccf Fpviol Faccerr Fblank Command buffers are fullFlash Status Register Fstat W1c Function Description Flash Command OperationsFlash Command Register Fcmd 15. Fcmd Field Descriptions Writing the Fcdiv Register 200 195 ⎟ 200 = 3% Start Command Write SequenceCommands Impossible ALL Program and Erase 16. Flash Command Description Flash CommandsErase Verify Command Fcmd NVM Program Command 11. Example Program Command Flow Burst Program Command Sequential Sector Erase CommandCommand Buffer Empty Programming 13. Example Sector Erase Command Flow Mass Erase Command 14. Example Mass Erase Command Flow Flash Access Violations Illegal Flash Operations Operating Modes Wait ModeBackground Debug Mode Flash Protection Violations Unsecuring the MCU using Backdoor Key Access Security Reset While Flash Command Active ResetsFlash Reset Sequence Program and Erase Times Security Stop SyncSet PRDIV8 and clock divider fields in CSR3 Device is unsecure Chapter Resets, Interrupts, and General System Control Microcontroller Reset Control Bits Clock Source COP Overflow Count COP Configuration OptionsComputer Operating Properly COP Watchdog Copclks Copt Pin Configuration Options Illegal Operation ResetIllegal Address Reset Interrupts and Exceptions Edge and Level Sensitivity Power-On Reset OperationLow-Voltage Detect LVD System External Interrupt Initialization LVD Interrupt Operation LVD Reset OperationPeripheral Clock Gating Low-Voltage Warning LVW Interrupt Operation Irqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack Interrupt Pin Request Status and Control Register IrqscIrqsc Register Field Descriptions Irqpdd System Reset Status Register SRS POR System Options Register 1 SOPT1 POR LVR System Options Register 2 SOPT2 SOPT1 Register Field Descriptions SPI1PS SPSCLK1 MOSI1 MISO1 SS1 System Device Identification Register SDIDH, SdidlSOPT2 Register Field Descriptions IIC1PS SDA1 SCL1 Sdidh Register Field Descriptions Sdidl Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack SPMSC1 Register Field Descriptions LPR Lprs Lpwui Ppde Ppdc Ppdack SPMSC2 Register Field Descriptions Lvwf 11. LVD and LVW Trip Point Typical Values1Lvwf Lvdv Lvwv Lvwie Lvdvlvwv 12. SCGC1 Register Field Descriptions System Clock Gating Control 1 Register SCGC1System Clock Gating Control 2 Register SCGC2 TPM3 13. SCGC2 Register Field Descriptions RTC SPI2 SPI1FLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Chapter Parallel Input/Output Control Port Data and Data DirectionFreescale Semiconductor 113 Pull-up, Slew Rate, and Drive Strength Port Internal Pull-up EnablePort Slew Rate Enable Data Direction Control Port Data Register Port Read Port Data Set, Clear and Toggle Data Registers Port Drive Strength SelectFreescale Semiconductor 115 Port Data Set Registers V1 ColdFire Rapid Gpio FunctionalityKeyboard Interrupts Port Data Clear Registers Pull-up/Pull-down Resistors Edge Only SensitivityEdge and Level Sensitivity Freescale Semiconductor 117 Keyboard Interrupt Initialization Pin Behavior in Stop ModesParallel I/O, Keyboard Interrupt, and Pin Control Registers Port a Registers Port a Data Direction Register Ptadd Port a Pull Enable Register PtapePort a Data Register Ptad PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0 PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 Port a Slew Rate Enable Register PtasePort a Drive Strength Selection Register Ptads PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 Port B Data Direction Register Ptbdd Port B RegistersPort B Data Register Ptbd Ptads Register Field Descriptions Ptbdd Register Field Descriptions Port B Pull Enable Register PtbpePort B Slew Rate Enable Register Ptbse Ptbpe Register Field Descriptions Port C Data Register Ptcd Port C RegistersPort B Drive Strength Selection Register Ptbds 10. Ptbds Register Field Descriptions Port C Data Clear Register Ptcclr Port C Data Direction Register PtcddPort C Data Set Register Ptcset 12. Ptcdd Register Field Descriptions 14. Ptcclr Register Field Descriptions Port C Pull Enable Register PtcpePort C Toggle Register Ptctog 16. Ptcpe Register Field Descriptions Port C Drive Strength Selection Register Ptcds Port C Slew Rate Enable Register PtcsePort D Registers Port D Data Register Ptdd 19. Ptdd Register Field Descriptions Port D Pull Enable Register PtdpePort D Data Direction Register Ptddd 20. Ptddd Register Field Descriptions Port D Drive Strength Selection Register Ptdds Port D Slew Rate Enable Register PtdsePort E Registers Port E Data Register Pted 24. Pted Register Field Descriptions Port E Data Direction Register PteddPort E Data Set Register Pteset 25. Ptedd Register Field Descriptions Port E Toggle Register Ptetog Port E Pull Enable Register PtepePort E Data Clear Register Pteclr PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 29. Ptepe Register Field Descriptions Port E Slew Rate Enable Register PtesePort E Drive Strength Selection Register Pteds 30. Ptese Register Field Descriptions Port F Data Register Ptfd Port F Pull Enable Register PtfpePort F Registers Port F Data Direction Register Ptfdd 34. Ptfpe Register Field Descriptions Port F Slew Rate Enable Register PtfsePort F Drive Strength Selection Register Ptfds 35. Ptfse Register Field Descriptions Port G Data Direction Register Ptgdd Port G RegistersPort G Data Register Ptgd 36. Ptfds Register Field Descriptions Port G Drive Strength Selection Register Ptgds Port G Pull Enable Register PtgpePort G Slew Rate Enable Register Ptgse 39. Ptgpe Register Field Descriptions Port H Data Direction Register Pthdd Port H RegistersPort H Data Register Pthd 41. Ptgds Register Field Descriptions Port H Drive Strength Selection Register Pthds Port H Pull Enable Register PthpePort H Slew Rate Enable Register Pthse 44. Pthpe Register Field Descriptions Port J Registers Port J Data Register PtjdPort J Data Direction Register Ptjdd Port J Drive Strength Selection Register Ptjds Port J Pull Enable Register PtjpePort J Slew Rate Enable Register Ptjse 49. Ptjpe Register Field Descriptions 51. Ptjds Register Field Descriptions Keyboard Interrupt 1 KBI1 Registers10.1 KBI1 Interrupt Status and Control Register KBI1SC 52. KBI1 Pin Mapping Keyboard Interrupt 1 KBI2 Registers 10.2 KBI1 Interrupt Pin Select Register KBI1PE10.3 KBI1 Interrupt Edge Select Register KBI1ES 57. KBI2SC Register Field Descriptions 11.1 KBI2 Interrupt Status and Control Register KBI2SC11.2 KBI2 Interrupt Pin Select Register KBI2PE 58. KBI2PE Register Field Descriptions 11.3 KBI2 Interrupt Edge Select Register KBI2ES 59. KBI2ES Register Field DescriptionsFreescale Semiconductor 143 144 Freescale Semiconductor Chapter ColdFire Core Overview Memory Map/Register Description Data Registers D0-D7 Supervisor/User Access RegistersSupervisor Access Only Registers ColdFire Core Programming Model Address Registers A0-A6 Supervisor/User Stack Pointers A7 and OTHERA7Data Condition Code Register CCR Freescale Semiconductor 149 Program Counter PC Vector Base Register VBRCCR Field Descriptions CPU Configuration Register Cpucr Status Register SR SR Field DescriptionsBWD Instruction Enhancements over Revision Isaa Functional DescriptionInstruction Set Architecture Isac Instruction Description Exception Processing Overview Exception Vector Assignments Vector StackedAssignment Numbers Offset Hex Counter Numbers Offset Hex Counter Exception Stack Frame DefinitionAssignment SSP → Format Field Encodings Fault Status Encodings2.2 S08 and ColdFire Exception Processing Comparison FS30 Definition Exception Processing Comparison Attribute S08 V1 ColdFireRTI RTE Processor Exceptions Access Error ExceptionAddress Error Exception Freescale Semiconductor 159 Line OpMode Effective Address Illegal Instruction Exception10. ColdFire Opword Line Definition OpwordLine Instruction Class Privilege Violation Trace ExceptionFreescale Semiconductor 161 Unimplemented Line-F Opcode RTE and Format Error ExceptionUnimplemented Line-A Opcode Debug Interrupt Unsupported Instruction Exception Fault-on-Fault HaltTrap Instruction Exception Interrupt Exception BDM Load 0x60 D0 Store 0x40 D0 Reset ExceptionAccess User read-only BDM read-only VER REV 11. D0 Hardware Configuration Info Field Description 12. D1 Hardware Configuration Information Field Description FlashszSramsz 13. Misaligned Operand References Instruction Execution TimingTiming Assumptions Address10 Size Bus Additional Operations CR/W 15. Move Long Execution Times Move Instruction Execution Times14. Move Byte and Word Execution Times Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl Standard One Operand Instruction Execution Times 16. One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Standard Two Operand Instruction Execution Times 17. Two Operand Instruction Execution Times Miscellaneous Instruction Execution Times 18. Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Branch Instruction Execution Times 19. General Branch Instruction Execution Times20. Bcc Instruction Execution Times Chapter Interrupt Controller CF1INTC AttributeHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x150 Next SCI2rx 0x154 SCI2tx 0x158 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x1440x148 Next ACMPx 0x14C 0x180 Next Interrupt Source Number To V1 ColdFire coreFreescale Semiconductor 177 External Signal Description Memory Map and Register DefinitionModes of Operation Memory Map Intc Force Interrupt Register IntcfrcCF1INTC Memory Map Intcfrc Field Descriptions Intc Wake-up Control Register Intcwcr INTCPL6P7,6 Field DescriptionsFreescale Semiconductor 181 Intc Set Interrupt Force Register Intcsfrc Intcwcr Field DescriptionsENB Intccfrc Field Descriptions Intc Clear Interrupt Force Register IntccfrcIntcsfrc Field Descriptions Offset CF1INTCBASE + 0x1F Intccfrc Intc Software and Level-nIACK Registers n = 1,2,3,...,7 Vecn Swiack 10. Legend for Table Interrupt Request Level and Priority AssignmentsINTCSWIACK, INTCLVLnIACK Field Descriptions Priority within Level Midpoint 12. V1 ColdFire Interrupt Assignments TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovflTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Initialization Information Application InformationEmulation of the HCS08’s 1-Level IRQ Handling Using INTCPL6P7,6 Registers More on Software IACKsFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Chapter Rapid Gpio Rgpio Freescale Semiconductor 193 V1 ColdFire Core Freescale Semiconductor 195 OEP Dsoc IFPCore RAM Rgpio Pin Muxing + Pad Logic On-platform Bus RgpioModule RGPIODATA150 Detailed Signal Descriptions Rgpio Module External I/O SignalsRgpio Detailed Signal Descriptions Memory Map/Register Definition Rgpio Write Memory MapRgpio Read Memory Map Rgpiodir Field Descriptions Rgpio Data Direction RgpiodirRgpio Data Rgpiodata DIR Rgpio Pin Enable Rgpioenb Rgpio Clear Data Rgpioclr Rgpioclr Field Descriptions Rgpio Set Data RgpiosetRgpio Toggle Data Rgpiotog Rgpioset Field Descriptions TOG Application 1 Simple Square-Wave Generation10. Rgpiotog Field Descriptions Field Description 15-0 Rgpio Toggle Data 11. Square-Wave Output Performance 29x 12. Emulated SPI Performance using Gpio OutputsSPI Speed @ Relative CPU f = 50 MHz Freescale Semiconductor 205 206 Freescale Semiconductor Chapter Analog Comparator 3V ACMPVLPV1 Acmp Configuration InformationACMP/TPM Configuration Information Acmp Clock Gating Interrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Stop3 Mode Operation Block DiagramWait Mode Operation Stop2 Mode Operation Acbgs Acpe Register DefinitionStatus and Control Register ACMPxSC Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF Acme InterruptsACMPxSC Field Descriptions Acmod 214 Freescale Semiconductor Chapter Analog-to-Digital Converter S08ADC12V1 ADC Clock GatingFreescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 Alternate Clock Module ConfigurationsChannel Assignments ADC Channel Assignment Temperature Sensor Hardware Trigger 2provides a block diagram of the ADC module Freescale Semiconductor 219 Signal Properties Name FunctionAD27-AD0 Voltage Reference High Vrefh Analog Power VddadAnalog Ground Vssad Voltage Reference Low Vrefl Coco Input Channel SelectInput Select ADCSC2 Register Field Descriptions Status and Control Register 2 ADCSC2Data Result High Register Adcrh Adact ADR10 ADR9 ADR8 Data Result Low Register AdcrlCompare Value High Register Adccvh ADCV11 ADCV10 ADCV9 ADCV8 Adccfg Register Field Descriptions Configuration Register AdccfgCompare Value Low Register Adccvl Adlpc Conversion Modes Pin Control 1 Register APCTL1Clock Divide Select Input Clock Select Pin Control 2 Register APCTL2 10. APCTL1 Register Field DescriptionsADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 ADPC15 Pin Control 3 Register APCTL311. APCTL2 Register Field Descriptions ADPC23 ADPC20 12. APCTL3 Register Field DescriptionsADPC21 ADPC16 Hardware Trigger Clock Select and Divide ControlInput Select and Pin Control Conversion Control Aborting Conversions Initiating ConversionsCompleting Conversions Freescale Semiconductor 231 13. Total Conversion Time vs. Control Conditions Power ControlSample Time and Total Conversion Time Adiclk Adlsmp MCU Wait Mode Operation Automatic Compare Function Stop3 Mode With Adack Disabled MCU Stop3 Mode OperationMCU Stop2 Mode Operation Stop3 Mode With Adack Enabled Pseudo-Code Example ADC Module Initialization ExampleInitialization Sequence Freescale Semiconductor 235 COCO=1? External Pins and RoutingReset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No Yes Read Adcrh Then Adcrl To Clear Coco Bit Continue Analog Input Pins Analog Supply PinsAnalog Reference Pins Freescale Semiconductor 237 Pin Leakage Error Sources of ErrorSampling Error Noise-Induced Errors Lsb = Code Width and Quantization ErrorLinearity Errors Freescale Semiconductor 239 Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor External Oscillator Stop2 Mode ConsiderationsChapter Internal Clock Source S08ICSV3 Freescale Semiconductor 243 Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor HGO, RANGE, EREFS, ERCLKEN, Erefsten Freescale Semiconductor 247 2is the ICS block diagram ICS Register Summary FLL Bypassed Internal Low Power FbilpFLL Bypassed External Low Power Fbelp Rdiv Irefs Clks Rdiv Irefs Irclken Irefsten ICS Control Register 1 ICSC1ICSC1 Field Descriptions Reference Divide Factor ICSC2 Field Descriptions ICS Control Register 2 ICSC2ICS Trim Register Icstrm Bdiv Range HGO Erefs Erclken Erefsten Icssc Field Descriptions ICS Status and Control IcsscIcstrm Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRS 608 19.92 MHz Reference range FLL factor DCO range512 16 20 MHz 1024 32 40 MHz IREFS=1 CLKS=00 IREFS=0 Operational ModesFLL Engaged Internal FEI IREFS=0 CLKS=10 FLL Bypassed Internal FBI FLL Bypassed Internal Low Power FbilpFLL Engaged External FEE FLL Bypassed External FBE Bus Frequency Divider Mode SwitchingFLL Bypassed External Low Power Fbelp Stop Internal Reference Clock Low Power Bit UsageDCO Maximum Frequency with 32.768 kHz Oscillator External Reference Clock Fixed Frequency Clock Local Clock IIC1 Position Options Module ConfigurationChapter Inter-Integrated Circuit S08IICV2 SOPT2IIC1PS MCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SCL Serial Clock Line SDA Serial Data LineFreescale Semiconductor 263 Iica Field Descriptions IIC Address Register IicaIIC Frequency Divider Register Iicf = Unimplemented or Reserved Hold Times μs Iicf Field DescriptionsHold Time Values for 8 MHz Bus Speed Mult ICR SDA IIC Divider and Hold Values ICR SCL IIC Control Register IICC1 IICC1 Field Descriptions IIC Status Register Iics Iics Field DescriptionsTCF Iicd Field Descriptions IIC Data I/O Register IicdIIC Control Register 2 IICC2 Freescale Semiconductor 269 IIC Protocol IICC2 Field DescriptionsGcaen Start Signal Slave Address TransmissionFreescale Semiconductor 271 Arbitration Procedure Stop SignalRepeated Start Signal Data Transfer Clock Stretching Clock SynchronizationHandshaking Freescale Semiconductor 273 13.4.2 10-bit Address Master-Transmitter Addresses a Slave-ReceiverMaster-Receiver Addresses a Slave-Transmitter Byte Transfer Interrupt ResetsGeneral Call Address Address Detect Interrupt 276 Freescale Semiconductor Module Initialization Master Initialization/Application InformationModule Initialization Slave Module Use 12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor RTC Clock Sources Chapter Real-Time Counter S08RTCV1ADC Hardware Trigger RTC Modes of Operation Interrupt Vector MCF51QE128 Block Diagram Highlighting RTC Block and Pins Freescale Semiconductor 283 Active Background Mode Erclk RTC Register SummaryLPO Irclk RTC Prescaler Divide-by values RTC Status and Control Register RtcscRtcsc Field Descriptions Rtif Rtccnt Field Descriptions RTC Counter Register RtccntRTC Modulo Register Rtcmod Rtcmod Field Descriptions Rtcps RTC Operation ExamplePrescaler Period KHz Internal Clock MHz External Clock Rtclks = 0x52 0x53 0x54 0x55 0x00 0x01 Internal 1-kHz Clock Source RTC Clock Rtcps =Rtccnt Rtif Freescale Semiconductor 289 290 Freescale Semiconductor Chapter Serial Communications Interface S08SCIV4 SCI Clock GatingFreescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI SCI Receiver Block Diagram Freescale Semiconductor 297 SCI Baud Rate Registers SCIxBDH, SCIxBDL SCIxBDH Field DescriptionsLbkdie Loops Sciswai Rsrc Wake ILT SCI Control Register 1 SCIxC1SCIxBDL Field Descriptions Loops SCI Control Register 2 SCIxC2 SCIxC2 Field DescriptionsTIE SCI Status Register 1 SCIxS1 Tdre Rdrf Idle Parity error Framing errorNo parity error SCIxD Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF SCI Status Register 2 SCIxS2SCIxS2 Field Descriptions RXINV1 Txdir SCI Control Register 3 SCIxC3SCIxC3 Field Descriptions TXINV1 SCI Data Register SCIxD Baud Rate GenerationFreescale Semiconductor 305 Transmitter Functional Description Send Break and Queued Idle Break Character Length Receiver Functional DescriptionData Sampling Technique BRK13 Receiver Wakeup Operation Idle-Line Wakeup Interrupts and Status Flags Freescale Semiconductor 309 Additional SCI Functions Stop Mode OperationLoop Mode 15.3.5.1 8- and 9-Bit Data Modes Single-Wire Operation Freescale Semiconductor 311 312 Freescale Semiconductor Chapter Serial Peripheral Interface S08SPIV3 SPI Clock GatingFreescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor Block Diagrams SPI System Block DiagramFreescale Semiconductor 317 SPI Module Block Diagram SPI Baud Rate Generation Freescale Semiconductor 319 Miso Master Data In, Slave Data Out Spsck SPI Serial ClockMosi Master Data Out, Slave Data SS Slave Select SPI Control Register 1 SPIxC1 Modes of OperationSPI in Stop Modes SPIxC1 Field Descriptions SS Pin Function Master Mode Slave ModeSPI Control Register 2 SPIxC2 Modfen Ssoe SPIxC2 Register Field Descriptions SPI Stop in Wait ModeSPI Baud Rate Register SPIxBR Modfen Bidiroe Spiswai Sppr SPI Status Register SPIxSSPIxBR Register Field Descriptions SPR SPI Data Register SPIxD SPI Clock Formats 10. SPI Clock Formats Cpha = Freescale Semiconductor 327 SPI Interrupts 11. SPI Clock Formats Cpha = Mode Fault Detection Freescale Semiconductor 329 330 Freescale Semiconductor Chapter Timer/Pulse-Width Modulator S08TPMV3 TPM Clock GatingFreescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor TPM Block Diagram Freescale Semiconductor 337 Signal Description Extclk TPMxCHn TPM Channel n I/O Pins Extclk External Clock SourceFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TOF Toie Cpwms Clksb Clksa PS2 PS1 TPM Status and Control Register TPMxSCTPMxSC Field Descriptions TOF Prescale Factor Selection TPM Counter Registers TPMxCNTHTPMxCNTLTPM-Clock-Source Selection Clksbclksa TPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter TPM Counter Modulo Registers TPMxMODHTPMxMODLTPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter Freescale Semiconductor 343 TPMxMOD70 TPM Channel n Status and Control Register TPMxCnSCTPMxMOD158 CHnF CHnIE MSnB MSnA ELSnB ELSnA Mode, Edge, and Level Selection MSnBMSnA ELSnBELSnA Mode ConfigurationTPMxCnSC Field Descriptions Cpwms TPMxCnV158 TPM Channel Value Registers TPMxCnVHTPMxCnVLMode, Edge, and Level Selection TPMxCnV70 Counter Counter Clock SourceFreescale Semiconductor 347 Counter Overflow and Modulo Reset TPM Clock Source Selection Input Capture Mode Channel Mode SelectionManual Counter Reset Output Compare Mode Edge-Aligned PWM Mode 15. PWM Period and Pulse Width ELSnA=0 Center-Aligned PWM Mode Freescale Semiconductor 351 Reset Overview Description of Reset OperationGeneral Description of Interrupt Operation Timer Overflow Interrupt TOF DescriptionInterrupt Local Source Description Enable Interrupt Summary Channel Event Interrupt Description Center-Aligned PWM Case Chapter Version 1 ColdFire Debug CF1DEBUG Freescale Semiconductor 355 PST Version 1 ColdFire Core CF1CoreOEP Bkgd BDC Revision Modes of OperationsDebug Revision Summary Csrhrl CSR2D1HRL Core Status Command Set BDM Command TypesCommand Type Flash BDM? External Signal Descriptions Debug Module Signals DescriptionBDM GO DRc Register Name Width Access Reset Value Section Bits Debug Module Memory MapCPU Configuration/Status Register CSR CSR Field Descriptions Bstat FOF TRG Halt Bkpt HRL BKD IPWTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Extended Configuration/Status Register Xcsr Xcsr Reference SummaryMethod Reference Details Xcsr CPU Cstat Halt Stop Eseqc Clksw SEC Erase EnbdmApcsc Apce CPU State Eseqc W SEC RErase W Xcsr CSR2 Configuration/Status Register 2 CSR2CSR2 Reference Summary Syncpc Interval CSR2 Field Descriptions PSTBWA7 Pstb Valid Data Locations Oldest to Newest Pstbss Configuration/Status Register 3 CSR310. CSR3 Reference Summary Start Condition Stop Condition BDM Address Attribute Register Baar BFC Bfcdiv DIV8BFCDIV8 Address Attribute Trigger Register Aatr SZM TTM TMM Trigger Definition Register TDR Signal of the processor’s local busBDM memory commands Normal processor access Else Reserved SZM L2T L1T L2EDL2EA L1EA L2T Three bits disables the address breakpoint Program Counter Breakpoint/Mask Registers PBR0-3, PbmrNo inversion Invert data breakpoint comparators DRc 0x08 PBR0 Mask Reset15. PBR0 Field Descriptions DRc 0x09 Pbmr Abhr Address Breakpoint Registers ABLR, Abhr17. Pbmr Field Descriptions Ablr Data Breakpoint and Mask Registers DBR, Dbmr 19. Abhr Field Description21. Dbmr Field Descriptions Address1 Access Size Operand Location Background Debug Mode BDM22. Access Size and Operand Data Location Resulting Set of Possible Trigger Combinations Halt Source Halt Timing Description CPU Halt23. CPU Halt Sources Cpucrard = Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details 15. BDC Host-to-Target Serial Bit Timing Freescale Semiconductor 385 16. BDC Target-to-Host Serial Bit Timing Logic BDM Command Set Descriptions Freescale Semiconductor 387 Core Register Commands Miscellaneous CommandsMemory Commands PST Trace Buffer Read Commands CRG CRN 24. BDM Command Code Field DescriptionsCRG VBR Ackdisable BDM Command Set Summary25. BDM Command Summary Ackenable Readcreg ReaddregReadpstb Syncpc Writecreg 0x03 Disable host/target handshake protocol Always AvailableEnable host/target handshake protocol Always Available Freescale Semiconductor 393 Data7-0 Enter active background mode if enabled Non-intrusive0x32 Host → Target Memory data7-0 Target → 0x36 0x3A Memory 0x37 0x33Xcsrsb 0x3B 0x12 Memory 0x12 Memory data7-0Target 0x16 Memory Data15-8 Memory data7-0 Target → Host 0x16 Memory No operation Non-intrusive Read CPU control register Active Background 0x30 Address23-0 Read debug control register Non-intrusive0xA0+CRN Host → Target Dreg data Target Memory data7-0 Target → Host 0x39 0x310x35 0x50+CRN Host → Target Pstb data Read CSR2 Status Byte Always Available Read general-purpose CPU register Active BackgroundRead Xcsr Status Byte Always Available Read CSR3 Status Byte Always Available 0xC0+CRN Creg data Synchronize PC to PST/DDATA Signals Non-intrusiveWrite CPU control register Active Background Freescale Semiconductor 401 0x10 Address23-0 Memory Data7-0 Write debug control register Non-intrusive0x80+CRN Dreg data Host → target Write general-purpose CPU register Active Background Write CSR2 Status Byte Always Available Serial Interface Hardware Handshake ProtocolWrite Xcsr Status Byte Always Available Write CSR3 Status Byte Always Available 19. Target Acknowledge Pulse ACK Freescale Semiconductor 405 Hardware Handshake Abort Procedure 20. Handshake Protocol at Command Level 21signal timing is not drawn to scale Freescale Semiconductor 407 21. ACK Abort Procedure at the Command Level Real-Time Debug Support Real-Time Trace SupportFreescale Semiconductor 409 PST40 Definition Enter user mode26. Processor Status Encodings Instructions, generate different encodings Begin Execution of Taken Branch PST = 0x08-0x0BFreescale Semiconductor 411 23. Example JMP Instruction Output in Pstb PST Values Description Pstbpst PST Trace Buffer Pstb18.4.3.3 PST/DDATA Example Pstbddata Processor Status, Debug Data Definition PST/DDATA 27. PST/DDATA Specification for User-Mode InstructionsInstruction Operand Syntax Freescale Semiconductor 415 416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set No Connect GND ResetFreescale-Recommended BDM Pinout Freescale Semiconductor 419 420 Freescale Semiconductor MCF51QE128RM Rev to Rev Changes Appendix a Revision HistoryChanges between Rev and Rev Chapter Description Revision History Page How to Reach Us