Freescale Semiconductor MCF51QE128RM manual 13.4.2 10-bit Address

13.4.210-bit Address

For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing.

13.4.2.1Master-Transmitter Addresses a Slave-Receiver

The transfer direction is not changed (see Table 13-10). When a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. Only one slave finds a match and generates an acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition

(P) or a repeated start condition (Sr) followed by a different slave address.

S

Slave Address 1st 7 bits	R/W
11110 + AD10 + AD9	0

A1

Slave Address 2nd byte

AD[8:1]

A2 Data A

... Data A/A

P

Table 13-10. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address

After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt.

13.4.2.2Master-Receiver Addresses a Slave-Transmitter

The transfer direction is changed after the second R/W bit (see Table 13-11). Up to and including acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed before. This slave then checks whether the first seven bits of the first byte of the slave address following Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3. The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition (Sr) followed by a different slave address.

After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match.

Slave Address

R/W

Slave Address

Slave Address

R/W

S

1st 7 bits

A1

2nd byte

A2

Sr

1st 7 bits

A3

Data

A

...

Data

A

P

11110 + AD10 + AD9

0

AD[8:1]

11110 + AD10 + AD9

1

Table 13-11. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address

After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this interrupt.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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