Freescale Semiconductor MCF51QE128RM manual Typical IIC Interrupt Routine

Clear

IICIF

Y

Master

N

Mode

?

TX

Tx/Rx

RX

Y

Arbitration

?

Lost

?

Last Byte

N

Y

Clear ARBL

Transmitted

?

N

RXAK=0

Last

N

IAAS=1

Y

IAAS=1

N

Byte to Be Read

Y

?

?

?

?

Y

N

Y

N

Address Transfer

Data Transfer

Y

See Note 1

See Note 2

End of

2nd Last

Y

Y

(Read)

Addr Cycle

SRW=1

TX/RX

RX

Byte to Be Read

(Master Rx)

?

?

?

?

N

N

N (Write)

TX

Y

ACK from

Write Next

Generate

Set TX

Set TXACK =1

Stop Signal

Receiver

Byte to IICD

Mode

(MST = 0)

?

N

Write Data

Tx Next

Read Data

from IICD

to IICD

Byte

and Store

Switch to

Set RX

Switch to

Rx Mode

Mode

Rx Mode

Dummy Read

Generate

Read Data

Dummy Read

Dummy Read

Stop Signal

from IICD

from IICD

from IICD

from IICD

(MST = 0)

and Store

RTI

NOTES:

1.If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a general call address, then the general call must be handled by user software.

2.When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer

Figure 13-12. Typical IIC Interrupt Routine

MCF51QE128 MCU Series Reference Manual, Rev. 3

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