Mode Fault Detection | Freescale Semiconductor MCF51QE128RM guide

16.5.3Mode Fault Detection

A mode fault occurs and the mode fault flag (MODF) sets when a master SPI device detects an error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is configured as the mode fault input signal when MSTR and MODFEN is set, and SSOE is clear.

The mode fault detection feature is used in a system where more than one SPI device might become a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.

When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are disabled.

MODF is cleared by reading it while it is set, then writing to the SPIxC1 register. Software should verify the error condition has been corrected before changing the SPI back to master mode.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Freescale Semiconductor Chapter Resets, Interrupts, and General System Control Title Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Chapter Inter-Integrated Circuit S08IICV2 Section Number Title Real-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History Feature MCF51QE128 MCF51QE128 Series Features by MCU and PackageChapter Device Overview Devices in the MCF51QE128/64/32 Series Xosc MCU Block Diagram MCF51QE128/64/32 Block Diagram System Clocks V1 ColdFire CoreInternal Clock Source ICS Module Module Versions System Clock Distribution Simplified ICS Block Diagram Icsirclk ICS Modes of Operation FLL Bypassed Internal Low-Power FbilpFLL Engaged Internal FEI FLL Engaged External FEE Stop Stop FLL Bypassed External Low-Power Fbelp Get the latest version from freescale.com Get the latest version from freescale.com Device Pin Assignment Chapter Pins and Connections Pin Lqfp Pins in bold are added from the next smaller package Recommended System Connections Basic System Connections Oscillator PowerReset and Rsto Background / Mode Select BKGD/MS General-Purpose I/O and Peripheral Ports ADC Reference Pins VREFH, Vrefl Pin Pin Assignment by Package and Pin Sharing PriorityPriority Number Port Pin Alt Port Pin Alt Number Get the latest version from freescale.com Introduction FeaturesChapter Modes of Operation Overview MCF51QE128/64/32 Power Modes Conceptual Drawing PMC CPU / Power Mode Selections Stop3 Mode Regulator StateFull On Run Stop2 LPrun Transition # From Trigger Triggers for Transitions Shown in Figure Secure Mode Debug Mode Low-Power Run Mode LPrun Run ModeBDM in Low-Power Run Mode Run Modes Low-Power Wait Mode LPwait Wait ModeBDM in Low-Power Wait Mode Wait Modes Stop2 Mode Low-Range Oscillator Considerations for Stop2 Stop3 ModeStop4 Low Voltage Detect or BDM Enabled in Stop Mode Low-Power Mode Behavior On-Chip Peripheral Modules in Stop and Low-Power ModesAbbreviations used in Table CF1CORE COP BDCICS IRQ Get the latest version from freescale.com Get the latest version from freescale.com MCF51QE128/64/32 Memory Map Chapter MemoryKbytes RAM Register Addresses and Bit Assignments CPU Access Type Allowed by RegionRead Write Base Address Region Byte Long Byte ColdFire Memory Organization Direct-Page Register Summary Sheet 1 Register Address Name Direct-Page Register Summary Sheet 2 Direct-Page Register Summary Sheet 3 High-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 4 High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 High-Page Register Summary Sheet 5 Flash Module Reserved Memory LocationsReserved Flash Memory Addresses 0x0 0x1 0x2 0x3 0x0000040C 0x0 0x1 0x2 0x3 0x00000408Reserved Flash Memory Addresses Register Nvprot ColdFire Interrupt Controller Memory Map ColdFire Rapid Gpio Memory MapV1 ColdFire Rapid Gpio Memory Map V1 ColdFire Interrupt Controller Memory Map Flash RAMIntcsfrc Intccfrc Addresses Desired Value Values Programmed FeaturesLov-Voltage Programming Sequence Example Flash Clock Divider Register Fcdiv Register DescriptionsFlash Options Register Fopt and Nvopt Fcdiv Field Descriptions 10. Fopt Field Descriptions Flash Configuration Register Fcnfg 11. Fcnfg Field Descriptions Flash Protection Register Fprot and Nvprot12. Fprot Field Descriptions 13. Flash Protection Address Range 0x40 0x00-0x3F0x41 0x00000-0x1EFFF 0x42 Flash Status Register Fstat Command buffers are fullFcbef Fccf Fpviol Faccerr Fblank W1c Flash Command Register Fcmd Flash Command OperationsFunction Description 15. Fcmd Field Descriptions 200 195 ⎟ 200 = 3% Writing the Fcdiv Register Commands Impossible Command Write SequenceStart ALL Program and Erase Erase Verify Command Flash Commands16. Flash Command Description Fcmd NVM Program Command 11. Example Program Command Flow Burst Program Command Command Buffer Empty Sector Erase CommandSequential Programming 13. Example Sector Erase Command Flow 14. Example Mass Erase Command Flow Mass Erase Command Illegal Flash Operations Flash Access Violations Background Debug Mode Wait ModeOperating Modes Flash Protection Violations Security Unsecuring the MCU using Backdoor Key Access Flash Reset Sequence ResetsReset While Flash Command Active Program and Erase Times Security Set PRDIV8 and clock divider fields in CSR3 SyncStop Device is unsecure Microcontroller Reset Chapter Resets, Interrupts, and General System Control Computer Operating Properly COP Watchdog COP Configuration OptionsControl Bits Clock Source COP Overflow Count Copclks Copt Illegal Address Reset Illegal Operation ResetPin Configuration Options Interrupts and Exceptions Low-Voltage Detect LVD System Power-On Reset OperationEdge and Level Sensitivity External Interrupt Initialization Peripheral Clock Gating LVD Reset OperationLVD Interrupt Operation Low-Voltage Warning LVW Interrupt Operation Irqsc Register Field Descriptions Interrupt Pin Request Status and Control Register IrqscIrqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack Irqpdd POR System Reset Status Register SRS POR LVR System Options Register 1 SOPT1 SOPT1 Register Field Descriptions System Options Register 2 SOPT2 SOPT2 Register Field Descriptions System Device Identification Register SDIDH, SdidlSPI1PS SPSCLK1 MOSI1 MISO1 SS1 IIC1PS SDA1 SCL1 Lvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack Sdidh Register Field DescriptionsSdidl Register Field Descriptions LPR Lprs Lpwui Ppde Ppdc Ppdack SPMSC1 Register Field Descriptions SPMSC2 Register Field Descriptions Lvwf Lvdv Lvwv Lvwie 11. LVD and LVW Trip Point Typical Values1Lvwf Lvdvlvwv System Clock Gating Control 2 Register SCGC2 System Clock Gating Control 1 Register SCGC112. SCGC1 Register Field Descriptions TPM3 FLS 13. SCGC2 Register Field DescriptionsRTC SPI2 SPI1 Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Freescale Semiconductor 113 Chapter Parallel Input/Output ControlPort Data and Data Direction Port Slew Rate Enable Port Internal Pull-up EnablePull-up, Slew Rate, and Drive Strength Data Direction Control Port Data Register Port Read Freescale Semiconductor 115 Port Data Set, Clear and Toggle Data RegistersPort Drive Strength Select Keyboard Interrupts V1 ColdFire Rapid Gpio FunctionalityPort Data Set Registers Port Data Clear Registers Edge and Level Sensitivity Edge Only SensitivityPull-up/Pull-down Resistors Freescale Semiconductor 117 Parallel I/O, Keyboard Interrupt, and Pin Control Registers Pin Behavior in Stop ModesKeyboard Interrupt Initialization Port a Registers Port a Data Register Ptad Port a Pull Enable Register PtapePort a Data Direction Register Ptadd PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0 Port a Drive Strength Selection Register Ptads Port a Slew Rate Enable Register PtasePTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 Port B Data Register Ptbd Port B RegistersPort B Data Direction Register Ptbdd Ptads Register Field Descriptions Port B Slew Rate Enable Register Ptbse Port B Pull Enable Register PtbpePtbdd Register Field Descriptions Ptbpe Register Field Descriptions Port B Drive Strength Selection Register Ptbds Port C RegistersPort C Data Register Ptcd 10. Ptbds Register Field Descriptions Port C Data Set Register Ptcset Port C Data Direction Register PtcddPort C Data Clear Register Ptcclr 12. Ptcdd Register Field Descriptions Port C Toggle Register Ptctog Port C Pull Enable Register Ptcpe14. Ptcclr Register Field Descriptions 16. Ptcpe Register Field Descriptions Port D Registers Port C Slew Rate Enable Register PtcsePort C Drive Strength Selection Register Ptcds Port D Data Register Ptdd Port D Data Direction Register Ptddd Port D Pull Enable Register Ptdpe19. Ptdd Register Field Descriptions 20. Ptddd Register Field Descriptions Port E Registers Port D Slew Rate Enable Register PtdsePort D Drive Strength Selection Register Ptdds Port E Data Register Pted Port E Data Set Register Pteset Port E Data Direction Register Ptedd24. Pted Register Field Descriptions 25. Ptedd Register Field Descriptions Port E Data Clear Register Pteclr Port E Pull Enable Register PtepePort E Toggle Register Ptetog PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 Port E Drive Strength Selection Register Pteds Port E Slew Rate Enable Register Ptese29. Ptepe Register Field Descriptions 30. Ptese Register Field Descriptions Port F Registers Port F Pull Enable Register PtfpePort F Data Register Ptfd Port F Data Direction Register Ptfdd Port F Drive Strength Selection Register Ptfds Port F Slew Rate Enable Register Ptfse34. Ptfpe Register Field Descriptions 35. Ptfse Register Field Descriptions Port G Data Register Ptgd Port G RegistersPort G Data Direction Register Ptgdd 36. Ptfds Register Field Descriptions Port G Slew Rate Enable Register Ptgse Port G Pull Enable Register PtgpePort G Drive Strength Selection Register Ptgds 39. Ptgpe Register Field Descriptions Port H Data Register Pthd Port H RegistersPort H Data Direction Register Pthdd 41. Ptgds Register Field Descriptions Port H Slew Rate Enable Register Pthse Port H Pull Enable Register PthpePort H Drive Strength Selection Register Pthds 44. Pthpe Register Field Descriptions Port J Data Direction Register Ptjdd Port J RegistersPort J Data Register Ptjd Port J Slew Rate Enable Register Ptjse Port J Pull Enable Register PtjpePort J Drive Strength Selection Register Ptjds 49. Ptjpe Register Field Descriptions 10.1 KBI1 Interrupt Status and Control Register KBI1SC Keyboard Interrupt 1 KBI1 Registers51. Ptjds Register Field Descriptions 52. KBI1 Pin Mapping 10.3 KBI1 Interrupt Edge Select Register KBI1ES Keyboard Interrupt 1 KBI2 Registers10.2 KBI1 Interrupt Pin Select Register KBI1PE 11.2 KBI2 Interrupt Pin Select Register KBI2PE 11.1 KBI2 Interrupt Status and Control Register KBI2SC57. KBI2SC Register Field Descriptions 58. KBI2PE Register Field Descriptions Freescale Semiconductor 143 11.3 KBI2 Interrupt Edge Select Register KBI2ES59. KBI2ES Register Field Descriptions 144 Freescale Semiconductor Overview Chapter ColdFire Core Memory Map/Register Description Supervisor Access Only Registers Supervisor/User Access RegistersData Registers D0-D7 ColdFire Core Programming Model Data Address Registers A0-A6Supervisor/User Stack Pointers A7 and OTHERA7 Freescale Semiconductor 149 Condition Code Register CCR CCR Field Descriptions Program Counter PCVector Base Register VBR CPU Configuration Register Cpucr BWD Status Register SRSR Field Descriptions Instruction Set Architecture Isac Functional DescriptionInstruction Enhancements over Revision Isaa Instruction Description Exception Processing Overview Assignment Numbers Offset Hex Counter Exception Vector AssignmentsVector Stacked Assignment Exception Stack Frame DefinitionNumbers Offset Hex Counter SSP → 2.2 S08 and ColdFire Exception Processing Comparison Fault Status EncodingsFormat Field Encodings FS30 Definition RTI RTE Exception Processing ComparisonAttribute S08 V1 ColdFire Address Error Exception Access Error ExceptionProcessor Exceptions Freescale Semiconductor 159 10. ColdFire Opword Line Definition Illegal Instruction ExceptionLine OpMode Effective Address OpwordLine Instruction Class Freescale Semiconductor 161 Privilege ViolationTrace Exception Unimplemented Line-A Opcode RTE and Format Error ExceptionUnimplemented Line-F Opcode Debug Interrupt Trap Instruction Exception Fault-on-Fault HaltUnsupported Instruction Exception Interrupt Exception Access User read-only BDM read-only Reset ExceptionBDM Load 0x60 D0 Store 0x40 D0 VER REV 11. D0 Hardware Configuration Info Field Description Sramsz 12. D1 Hardware Configuration Information Field DescriptionFlashsz Timing Assumptions Instruction Execution Timing13. Misaligned Operand References Address10 Size Bus Additional Operations CR/W 14. Move Byte and Word Execution Times Move Instruction Execution Times15. Move Long Execution Times Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl Effective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Standard One Operand Instruction Execution Times16. One Operand Instruction Execution Times 17. Two Operand Instruction Execution Times Standard Two Operand Instruction Execution Times Opcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Miscellaneous Instruction Execution Times18. Miscellaneous Instruction Execution Times 20. Bcc Instruction Execution Times Branch Instruction Execution Times19. General Branch Instruction Execution Times HCS08 Chapter Interrupt Controller CF1INTCAttribute Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x148 Next ACMPx 0x14C 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x1440x150 Next SCI2rx 0x154 SCI2tx 0x158 0x180 Next Freescale Semiconductor 177 Interrupt Source NumberTo V1 ColdFire core Modes of Operation External Signal DescriptionMemory Map and Register Definition CF1INTC Memory Map Memory MapIntc Force Interrupt Register Intcfrc Intcfrc Field Descriptions Freescale Semiconductor 181 Intc Wake-up Control Register IntcwcrINTCPL6P7,6 Field Descriptions ENB Intc Set Interrupt Force Register IntcsfrcIntcwcr Field Descriptions Intcsfrc Field Descriptions Intc Clear Interrupt Force Register IntccfrcIntccfrc Field Descriptions Offset CF1INTCBASE + 0x1F Intccfrc Vecn Swiack Intc Software and Level-nIACK Registers n = 1,2,3,...,7 INTCSWIACK, INTCLVLnIACK Field Descriptions Interrupt Request Level and Priority Assignments10. Legend for Table Priority within Level Midpoint TPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl 12. V1 ColdFire Interrupt AssignmentsTPM1ch0 TPM1ch1 TPM1ch2 TPM1ovfl Handling of Non-Maskable Level 7 Interrupt Requests Emulation of the HCS08’s 1-Level IRQ Handling Initialization InformationApplication Information Freescale Semiconductor 189 Using INTCPL6P7,6 RegistersMore on Software IACKs ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Freescale Semiconductor 193 Chapter Rapid Gpio Rgpio V1 ColdFire Core Freescale Semiconductor 195 Core IFPOEP Dsoc RAM Rgpio Module RgpioPin Muxing + Pad Logic On-platform Bus RGPIODATA150 Rgpio Detailed Signal Descriptions Detailed Signal DescriptionsRgpio Module External I/O Signals Rgpio Read Memory Map Memory Map/Register DefinitionRgpio Write Memory Map Rgpio Data Rgpiodata Rgpio Data Direction RgpiodirRgpiodir Field Descriptions DIR Rgpio Clear Data Rgpioclr Rgpio Pin Enable Rgpioenb Rgpio Toggle Data Rgpiotog Rgpio Set Data RgpiosetRgpioclr Field Descriptions Rgpioset Field Descriptions 10. Rgpiotog Field Descriptions Application 1 Simple Square-Wave GenerationTOG Field Description 15-0 Rgpio Toggle Data 11. Square-Wave Output Performance SPI Speed @ Relative CPU f = 50 MHz 12. Emulated SPI Performance using Gpio Outputs29x Freescale Semiconductor 205 206 Freescale Semiconductor ACMP/TPM Configuration Information Acmp Configuration InformationChapter Analog Comparator 3V ACMPVLPV1 Acmp Clock Gating Interrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Wait Mode Operation Block DiagramStop3 Mode Operation Stop2 Mode Operation Status and Control Register ACMPxSC Register DefinitionAcbgs Acpe Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF ACMPxSC Field Descriptions InterruptsAcme Acmod 214 Freescale Semiconductor Freescale Semiconductor 215 Chapter Analog-to-Digital Converter S08ADC12V1ADC Clock Gating Analog-to-Digital Converter S08ADC12V1 Channel Assignments Module ConfigurationsAlternate Clock ADC Channel Assignment Hardware Trigger Temperature Sensor Freescale Semiconductor 219 2provides a block diagram of the ADC module AD27-AD0 Signal PropertiesName Function Analog Ground Vssad Analog Power VddadVoltage Reference High Vrefh Voltage Reference Low Vrefl Input Select CocoInput Channel Select Data Result High Register Adcrh Status and Control Register 2 ADCSC2ADCSC2 Register Field Descriptions Adact Compare Value High Register Adccvh Data Result Low Register AdcrlADR10 ADR9 ADR8 ADCV11 ADCV10 ADCV9 ADCV8 Compare Value Low Register Adccvl Configuration Register AdccfgAdccfg Register Field Descriptions Adlpc Clock Divide Select Pin Control 1 Register APCTL1Conversion Modes Input Clock Select ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 Pin Control 2 Register APCTL210. APCTL1 Register Field Descriptions 11. APCTL2 Register Field Descriptions Pin Control 3 Register APCTL3ADPC15 ADPC23 ADPC21 12. APCTL3 Register Field DescriptionsADPC20 ADPC16 Input Select and Pin Control Clock Select and Divide ControlHardware Trigger Conversion Control Completing Conversions Initiating ConversionsAborting Conversions Freescale Semiconductor 231 Sample Time and Total Conversion Time Power Control13. Total Conversion Time vs. Control Conditions Adiclk Adlsmp Automatic Compare Function MCU Wait Mode Operation MCU Stop2 Mode Operation MCU Stop3 Mode OperationStop3 Mode With Adack Disabled Stop3 Mode With Adack Enabled Initialization Sequence ADC Module Initialization ExamplePseudo-Code Example Freescale Semiconductor 235 Reset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No External Pins and RoutingCOCO=1? Yes Read Adcrh Then Adcrl To Clear Coco Bit Continue Analog Reference Pins Analog Supply PinsAnalog Input Pins Freescale Semiconductor 237 Sampling Error Sources of ErrorPin Leakage Error Noise-Induced Errors Linearity Errors Code Width and Quantization ErrorLsb = Freescale Semiconductor 239 Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor Chapter Internal Clock Source S08ICSV3 Stop2 Mode ConsiderationsExternal Oscillator Freescale Semiconductor 243 Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor Freescale Semiconductor 247 HGO, RANGE, EREFS, ERCLKEN, Erefsten 2is the ICS block diagram FLL Bypassed External Low Power Fbelp FLL Bypassed Internal Low Power FbilpICS Register Summary Rdiv Irefs ICSC1 Field Descriptions ICS Control Register 1 ICSC1Clks Rdiv Irefs Irclken Irefsten Reference Divide Factor ICS Trim Register Icstrm ICS Control Register 2 ICSC2ICSC2 Field Descriptions Bdiv Range HGO Erefs Erclken Erefsten Icstrm Field Descriptions ICS Status and Control IcsscIcssc Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRS 512 16 20 MHz Reference range FLL factor DCO range608 19.92 MHz 1024 32 40 MHz FLL Engaged Internal FEI Operational ModesIREFS=1 CLKS=00 IREFS=0 IREFS=0 CLKS=10 FLL Engaged External FEE FLL Bypassed Internal Low Power FbilpFLL Bypassed Internal FBI FLL Bypassed External FBE FLL Bypassed External Low Power Fbelp Mode SwitchingBus Frequency Divider Stop DCO Maximum Frequency with 32.768 kHz Oscillator Low Power Bit UsageInternal Reference Clock External Reference Clock Local Clock Fixed Frequency Clock Chapter Inter-Integrated Circuit S08IICV2 Module ConfigurationIIC1 Position Options SOPT2IIC1PS MCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor Freescale Semiconductor 263 SCL Serial Clock LineSDA Serial Data Line IIC Frequency Divider Register Iicf IIC Address Register IicaIica Field Descriptions = Unimplemented or Reserved Hold Time Values for 8 MHz Bus Speed Iicf Field DescriptionsHold Times μs Mult ICR SDA ICR SCL IIC Divider and Hold Values IICC1 Field Descriptions IIC Control Register IICC1 TCF IIC Status Register IicsIics Field Descriptions IIC Control Register 2 IICC2 IIC Data I/O Register IicdIicd Field Descriptions Freescale Semiconductor 269 Gcaen IIC ProtocolIICC2 Field Descriptions Freescale Semiconductor 271 Start SignalSlave Address Transmission Repeated Start Signal Stop SignalArbitration Procedure Data Transfer Handshaking Clock SynchronizationClock Stretching Freescale Semiconductor 273 Master-Receiver Addresses a Slave-Transmitter 13.4.2 10-bit AddressMaster-Transmitter Addresses a Slave-Receiver General Call Address ResetsByte Transfer Interrupt Address Detect Interrupt 276 Freescale Semiconductor Module Initialization Slave Initialization/Application InformationModule Initialization Master Module Use 12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor ADC Hardware Trigger Chapter Real-Time Counter S08RTCV1RTC Clock Sources RTC Modes of Operation Interrupt Vector Freescale Semiconductor 283 MCF51QE128 Block Diagram Highlighting RTC Block and Pins Active Background Mode LPO RTC Register SummaryErclk Irclk Rtcsc Field Descriptions RTC Status and Control Register RtcscRTC Prescaler Divide-by values Rtif RTC Modulo Register Rtcmod RTC Counter Register RtccntRtccnt Field Descriptions Rtcmod Field Descriptions Prescaler Period RTC Operation ExampleRtcps KHz Internal Clock MHz External Clock Rtclks = Rtccnt Rtif Internal 1-kHz Clock Source RTC Clock Rtcps =0x52 0x53 0x54 0x55 0x00 0x01 Freescale Semiconductor 289 290 Freescale Semiconductor Freescale Semiconductor 291 Chapter Serial Communications Interface S08SCIV4SCI Clock Gating Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI Freescale Semiconductor 297 SCI Receiver Block Diagram Lbkdie SCI Baud Rate Registers SCIxBDH, SCIxBDLSCIxBDH Field Descriptions SCIxBDL Field Descriptions SCI Control Register 1 SCIxC1Loops Sciswai Rsrc Wake ILT Loops TIE SCI Control Register 2 SCIxC2SCIxC2 Field Descriptions Tdre Rdrf Idle SCI Status Register 1 SCIxS1 No parity error Framing errorParity error SCIxD SCIxS2 Field Descriptions SCI Status Register 2 SCIxS2Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF RXINV1 SCIxC3 Field Descriptions SCI Control Register 3 SCIxC3Txdir TXINV1 Freescale Semiconductor 305 SCI Data Register SCIxDBaud Rate Generation Send Break and Queued Idle Transmitter Functional Description Data Sampling Technique Receiver Functional DescriptionBreak Character Length BRK13 Idle-Line Wakeup Receiver Wakeup Operation Freescale Semiconductor 309 Interrupts and Status Flags Loop Mode Stop Mode OperationAdditional SCI Functions 15.3.5.1 8- and 9-Bit Data Modes Freescale Semiconductor 311 Single-Wire Operation 312 Freescale Semiconductor Freescale Semiconductor 313 Chapter Serial Peripheral Interface S08SPIV3SPI Clock Gating MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor Freescale Semiconductor 317 Block DiagramsSPI System Block Diagram SPI Module Block Diagram Freescale Semiconductor 319 SPI Baud Rate Generation Mosi Master Data Out, Slave Data Spsck SPI Serial ClockMiso Master Data In, Slave Data Out SS Slave Select SPI in Stop Modes Modes of OperationSPI Control Register 1 SPIxC1 SPIxC1 Field Descriptions SPI Control Register 2 SPIxC2 Master Mode Slave ModeSS Pin Function Modfen Ssoe SPI Baud Rate Register SPIxBR SPI Stop in Wait ModeSPIxC2 Register Field Descriptions Modfen Bidiroe Spiswai SPIxBR Register Field Descriptions SPI Status Register SPIxSSppr SPR SPI Data Register SPIxD SPI Clock Formats Freescale Semiconductor 327 10. SPI Clock Formats Cpha = 11. SPI Clock Formats Cpha = SPI Interrupts Freescale Semiconductor 329 Mode Fault Detection 330 Freescale Semiconductor Freescale Semiconductor 331 Chapter Timer/Pulse-Width Modulator S08TPMV3TPM Clock Gating Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor Freescale Semiconductor 337 TPM Block Diagram Extclk Signal Description Freescale Semiconductor 339 TPMxCHn TPM Channel n I/O PinsExtclk External Clock Source High-True Pulse of an Edge-Aligned PWM TPMxSC Field Descriptions TPM Status and Control Register TPMxSCTOF Toie Cpwms Clksb Clksa PS2 PS1 TOF TPM-Clock-Source Selection TPM Counter Registers TPMxCNTHTPMxCNTLPrescale Factor Selection Clksbclksa TPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter TPM Counter Modulo Registers TPMxMODHTPMxMODLTPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter Freescale Semiconductor 343 TPMxMOD158 TPM Channel n Status and Control Register TPMxCnSCTPMxMOD70 CHnF CHnIE MSnB MSnA ELSnB ELSnA TPMxCnSC Field Descriptions MSnBMSnA ELSnBELSnA Mode ConfigurationMode, Edge, and Level Selection Cpwms Mode, Edge, and Level Selection TPM Channel Value Registers TPMxCnVHTPMxCnVLTPMxCnV158 TPMxCnV70 Freescale Semiconductor 347 CounterCounter Clock Source TPM Clock Source Selection Counter Overflow and Modulo Reset Manual Counter Reset Channel Mode SelectionInput Capture Mode Output Compare Mode 15. PWM Period and Pulse Width ELSnA=0 Edge-Aligned PWM Mode Freescale Semiconductor 351 Center-Aligned PWM Mode General Reset OverviewDescription of Reset Operation Interrupt Local Source Description Enable Timer Overflow Interrupt TOF DescriptionDescription of Interrupt Operation Interrupt Summary Center-Aligned PWM Case Channel Event Interrupt Description Freescale Semiconductor 355 Chapter Version 1 ColdFire Debug CF1DEBUG OEP Version 1 ColdFire Core CF1CorePST Bkgd BDC Debug Revision Summary Modes of OperationsRevision Csrhrl CSR2D1HRL Command Type Flash BDM Command TypesCore Status Command Set BDM? BDM GO External Signal DescriptionsDebug Module Signals Description CPU DRc Register Name Width Access Reset Value Section BitsDebug Module Memory Map Configuration/Status Register CSR TRC DDC UHE BTB NPL IPI SSM FID DDH CSR Field DescriptionsBstat FOF TRG Halt Bkpt HRL BKD IPW TRC Method Reference Details Extended Configuration/Status Register XcsrXcsr Reference Summary Apcsc Apce CPU Cstat Halt Stop Eseqc Clksw SEC Erase EnbdmXcsr CPU State Erase W Eseqc WSEC R CSR2 Reference Summary Configuration/Status Register 2 CSR2Xcsr CSR2 Syncpc Interval CSR2 Field Descriptions Pstb Valid Data Locations Oldest to Newest PSTBWA7 10. CSR3 Reference Summary Configuration/Status Register 3 CSR3Pstbss Start Condition Stop Condition BFCDIV8 BDM Address Attribute Register BaarBFC Bfcdiv DIV8 SZM TTM TMM Address Attribute Trigger Register Aatr BDM memory commands Normal processor access Else Reserved Signal of the processor’s local busTrigger Definition Register TDR SZM L2EA L2EDL2T L1T L1EA L2T No inversion Invert data breakpoint comparators Three bits disables the address breakpointProgram Counter Breakpoint/Mask Registers PBR0-3, Pbmr 15. PBR0 Field Descriptions Mask ResetDRc 0x08 PBR0 DRc 0x09 Pbmr 17. Pbmr Field Descriptions Address Breakpoint Registers ABLR, AbhrAbhr Ablr 21. Dbmr Field Descriptions Data Breakpoint and Mask Registers DBR, Dbmr19. Abhr Field Description 22. Access Size and Operand Data Location Background Debug Mode BDMAddress1 Access Size Operand Location Resulting Set of Possible Trigger Combinations 23. CPU Halt Sources CPU HaltHalt Source Halt Timing Description Cpucrard = Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details Freescale Semiconductor 385 15. BDC Host-to-Target Serial Bit Timing 16. BDC Target-to-Host Serial Bit Timing Logic Freescale Semiconductor 387 BDM Command Set Descriptions Memory Commands Miscellaneous CommandsCore Register Commands PST Trace Buffer Read Commands CRG 24. BDM Command Code Field DescriptionsCRG CRN VBR 25. BDM Command Summary BDM Command Set SummaryAckdisable Ackenable Readpstb ReadcregReaddreg Writecreg Syncpc Enable host/target handshake protocol Always Available Disable host/target handshake protocol Always Available0x03 Freescale Semiconductor 393 0x32 Host → Target Memory data7-0 Target → 0x36 Enter active background mode if enabled Non-intrusiveData7-0 0x3A Memory Xcsrsb 0x330x37 0x3B Target 0x16 Memory Data15-8 Memory data7-0 0x12 Memory data7-00x12 Memory Target → Host 0x16 Memory Read CPU control register Active Background No operation Non-intrusive 0xA0+CRN Host → Target Dreg data Read debug control register Non-intrusive0x30 Address23-0 Target Memory data7-0 Target → Host 0x35 0x310x39 0x50+CRN Host → Target Pstb data Read Xcsr Status Byte Always Available Read general-purpose CPU register Active BackgroundRead CSR2 Status Byte Always Available Read CSR3 Status Byte Always Available Write CPU control register Active Background Synchronize PC to PST/DDATA Signals Non-intrusive0xC0+CRN Creg data Freescale Semiconductor 401 0x80+CRN Dreg data Write debug control register Non-intrusive0x10 Address23-0 Memory Data7-0 Host → target Write general-purpose CPU register Active Background Write Xcsr Status Byte Always Available Serial Interface Hardware Handshake ProtocolWrite CSR2 Status Byte Always Available Write CSR3 Status Byte Always Available Freescale Semiconductor 405 19. Target Acknowledge Pulse ACK 20. Handshake Protocol at Command Level Hardware Handshake Abort Procedure Freescale Semiconductor 407 21signal timing is not drawn to scale 21. ACK Abort Procedure at the Command Level Freescale Semiconductor 409 Real-Time Debug SupportReal-Time Trace Support 26. Processor Status Encodings Enter user modePST40 Definition Instructions, generate different encodings Freescale Semiconductor 411 Begin Execution of Taken Branch PST =0x08-0x0B PST Values Description 23. Example JMP Instruction Output in Pstb 18.4.3.3 PST/DDATA Example PST Trace Buffer PstbPstbpst Pstbddata Processor Status, Debug Data Definition Instruction Operand Syntax 27. PST/DDATA Specification for User-Mode InstructionsPST/DDATA Freescale Semiconductor 415 416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set Freescale-Recommended BDM Pinout GND ResetNo Connect Freescale Semiconductor 419 420 Freescale Semiconductor Changes between Rev and Rev Appendix a Revision HistoryMCF51QE128RM Rev to Rev Changes Chapter Description Revision History Page How to Reach Us