Freescale Semiconductor MCF51QE128RM manual 11.1.5

Section Number			Title	Page
	11.1.5	Block Diagram		219
11.2	External Signal Description			220
	11.2.1	Analog Power (VDDAD)		221
	11.2.2	Analog Ground (VSSAD)		221
	11.2.3	Voltage Reference High (VREFH)		221
	11.2.4	Voltage Reference Low (VREFL)		221
	11.2.5	Analog Channel Inputs (ADx)		221
11.3	Register Definition		........................................................................................................................	221
	11.3.1	Status and Control Register 1 (ADCSC1)		221
	11.3.2	Status and Control Register 2 (ADCSC2)		223
	11.3.3	Data Result High Register (ADCRH)		223
	11.3.4	Data Result Low Register (ADCRL)		224
	11.3.5	Compare Value High Register (ADCCVH)		224
	11.3.6 Compare Value Low Register (ADCCVL)			225
	11.3.7	Configuration Register (ADCCFG)		225
	11.3.8	Pin Control 1 Register (APCTL1)		226
	11.3.9	Pin Control 2 Register (APCTL2)		227
	11.3.10Pin Control 3 Register (APCTL3)			228
11.4	Functional Description			229
	11.4.1	Clock Select and Divide Control		230
	11.4.2	Input Select and Pin Control		230
	11.4.3	Hardware Trigger		230
	11.4.4	Conversion Control		230
		11.4.4.1	Initiating Conversions	231
		11.4.4.2	Completing Conversions	231
		11.4.4.3	Aborting Conversions	231
		11.4.4.4	Power Control	232
		11.4.4.5 Sample Time and Total Conversion Time		232
	11.4.5	Automatic Compare Function		233
	11.4.6 MCU Wait Mode Operation			233
	11.4.7 MCU Stop3 Mode Operation			234
		11.4.7.1 Stop3 Mode With ADACK Disabled		234
		11.4.7.2 Stop3 Mode With ADACK Enabled		234
	11.4.8 MCU Stop2 Mode Operation			234
11.5	Initialization Information			234
	11.5.1	ADC Module Initialization Example		235
		11.5.1.1	Initialization Sequence	235
		11.5.1.2	Pseudo-Code Example	235
11.6	Application Information			236
	11.6.1	External Pins and Routing		236
		11.6.1.1	Analog Supply Pins	237
		11.6.1.2	Analog Reference Pins	237
			MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor				15
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