Freescale Semiconductor MCF51QE128RM manual Rgpio Data Direction Rgpiodir, Rgpio Data Rgpiodata

Chapter 9 Rapid GPIO (RGPIO)

9.3.2Register Descriptions

The RGPIO module provides 16 bits of high-speed general-purpose input/output functionality via a connection to the processor’s 32-bit local bus. As a result, the RGPIO programming model is defined with a 32-bit organization. The basic size of each program-visible register is 16 bits, but the programming model may be referenced using byte (8-bit), word (16-bit), or longword (32-bit) accesses. Performance is typically maximized using 32-bit accesses.

9.3.2.1RGPIO Data Direction (RGPIO_DIR)

The RGPIO_DIR register defines whether a properly-enabled RGPIO pin is configured as an input or output. The RGPIO_DIR register is read/write. At reset, all bits in the RGPIO_DIR are cleared. Setting any bit in the RGPIO_DIR register configures a properly-enabled RGPIO port pin as an output. Clearing any bit in the RGPIO_DIR register configures a properly-enabled RGPIO port pin as an input.

Offset: RGPIO_Base + 0x0 (RGPIO_DIR)

RGPIO_Base + 0x8

RGPIO_Base + 0xC

15 14 13 12 11 10 9 8

7 6 5 4

Access: Read/write

Read-only

Read-only

3 2 1 0

R

W

Reset

DIR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

	Figure 9-4. RGPIO Data Direction Register (RGPIO_DIR)
	Table 9-5. RGPIO_DIR Field Descriptions
Field	Description
15–0	RGPIO data direction.
DIR	0 A properly-enabled RGPIO pin is configured as an input.

1A properly-enabled RGPIO pin is configured as an output.

9.3.2.2RGPIO Data (RGPIO_DATA)

The RGPIO_DATA register specifies the write data for a properly-enabled RGPIO output pin or the sampled read data value for a properly-enabled input pin. An attempted read of the RGPIO_DATA register returns undefined data for disabled pins because the data value is dependent on the device-level pin muxing and pad implementation. The RGPIO_DATA register is read/write. At reset, all bits in the RGPIO_DATA registers are cleared.

Reading the RGPIO_DATA register returns the current port values of properly-enabled pins. To set bits in a RGPIO_DATA register, directly set the RGPIO_DATA bits or set the corresponding bits in the RGPIO_SET register. To clear bits in the RGPIO_DATA register, directly clear the RGPIO_DATA bits, or clear the corresponding bits in the RGPIO_CLR register. Setting a bit in the RGPIO_TOG register inverts (toggles) the state of the corresponding bit in the RGPIO_DATA register.

MCF51QE128 MCU Series Reference Manual, Rev. 3

200 Freescale Semiconductor

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