Chapter 8 Interrupt Controller (CF1_INTC)

Table 8-11. V1 ColdFire [Level][Priority within Level] Matrix Interrupt Assignments (continued)

 

 

 

 

 

 

 

 

 

 

 

 

Priority within Level

 

 

 

 

 

 

 

 

 

 

 

 

Level

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

6

 

5

4

 

Midpoint

 

3

 

2

 

1

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

IICx1

 

KBIx2

 

ADC

ACMPx3

 

 

 

 

force_lvl3

15

 

79

16

 

80

17

 

81

18

 

82

 

 

 

 

FRC[36]

 

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

SCI2_err

SCI2_rx

SCI2_tx

 

 

RTC

force_lvl2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

83

20

 

84

21

 

85

 

22

 

86

 

FRC[37]

 

101

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

TPM3_ch0

TPM3_ch1

TPM3_ch2

TPM3_ch3

TPM3_ch4

TPM3_ch5

TPM3_ovfl

force_lvl1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

87

24

 

88

25

 

89

26

 

90

27

 

91

28

 

92

29

 

93

 

FRC[38]

 

102

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1There are two I2C modules on-chip. They share a common interrupt vector.

2The keyboard features are available on GPIO ports B and D. The two modules share a common interrupt vector.

3There are two analog comparator modules on-chip. They share a common interrupt vector.

Table 8-12presents the same information on interrupt request assignments, but from the highest priority request to the lowest.

Table 8-12. V1 ColdFire Interrupt Assignments

IRQ Source

Level

Priority

Interrupt Source

Vector

within Level

Number

 

 

 

 

 

 

 

 

IRQ_pin

7

mid

0

64

 

 

 

 

 

low_voltage

7

3

1

65

 

 

 

 

 

force_lvl7

7

0

INTC_FRC[32]

96

 

 

 

 

 

remapped_l6p7

6

7

INTC_PL6P7

*

 

 

 

 

 

remapped_l6p6

6

6

INTC_PL6P6

*

 

 

 

 

 

TPM1_ch0

6

5

2

66

 

 

 

 

 

TPM1_ch1

6

4

3

67

 

 

 

 

 

TPM1_ch2

6

3

4

68

 

 

 

 

 

TPM1_ovfl

6

1

5

69

 

 

 

 

 

force_lvl6

6

0

INTC_FRC[33]

97

 

 

 

 

 

TPM2_ch0

5

7

6

70

 

 

 

 

 

TPM2_ch1

5

6

7

71

 

 

 

 

 

TPM2_ch2

5

5

8

72

 

 

 

 

 

TPM2_ovfl

5

1

9

73

 

 

 

 

 

force_lvl5

5

0

INTC_FRC[34]

98

 

 

 

 

 

SPI2

4

7

10

74

 

 

 

 

 

SPI1

4

6

11

75

 

 

 

 

 

SCI1_err

4

5

12

76

 

 

 

 

 

 

MCF51QE128 MCU Series Reference Manual, Rev. 3

186

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Freescale Semiconductor MCF51QE128RM manual 12. V1 ColdFire Interrupt Assignments, TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovfl