Freescale Semiconductor MCF51QE128RM manual BDC Host-to-Target Serial Bit Timing

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period.

BDC CLOCK (TARGET MCU)

HOST

TRANSMIT 1

HOST

TRANSMIT 0

SYNCHRONIZATION UNCERTAINTY

PERCEIVED START OF BIT TIME

10 CYCLES

EARLIEST START OF NEXT BIT

TARGET SENSES BIT LEVEL

Figure 18-15. BDC Host-to-Target Serial Bit Timing

Figure 18-16shows the host receiving a logic 1 from the target MCU. Because the host is asynchronous to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The host should sample the bit level about 10 cycles after it started the bit time.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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