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Freescale Semiconductor MCF51QE128RM manual IIC Protocol, IICC2 Field Descriptions, Gcaen

Models: MCF51QE128RM

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		Table 13-9. IICC2 Field Descriptions

Field		Description

7	General Call Address Enable. The GCAEN bit enables or disables general call address.
GCAEN	0	General call address is disabled
	1	General call address is enabled

6	Address Extension. The ADEXT bit controls the number of bits used for the slave address.
ADEXT	0	7-bit address scheme
	1	10-bit address scheme

2–0	Slave Address. The AD[10:8] field contains the upper three bits of the slave address in the 10-bit address
AD[10:8]	scheme. This field is only valid when the ADEXT bit is set.

13.4Functional Description

This section provides a complete functional description of the IIC module.

13.4.1IIC Protocol

The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.

Normally, a standard communication is composed of four parts:

•Start signal

•Slave address transmission

•Data transfer

•Stop signal

The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication is described briefly in the following sections and illustrated in Figure 13-9.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual IIC Protocol, IICC2 Field Descriptions, Gcaen

Contents

MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Chapter Resets, Interrupts, and General System Control Freescale SemiconductorTitle Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Section Number Title Chapter Inter-Integrated Circuit S08IICV2Real-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History Chapter Device Overview MCF51QE128 Series Features by MCU and PackageFeature MCF51QE128 Devices in the MCF51QE128/64/32 SeriesMCU Block Diagram XoscMCF51QE128/64/32 Block Diagram Internal Clock Source ICS Module V1 ColdFire CoreSystem Clocks Module VersionsSimplified ICS Block Diagram System Clock DistributionIcsirclk FLL Engaged Internal FEI FLL Bypassed Internal Low-Power FbilpICS Modes of Operation FLL Engaged External FEEFLL Bypassed External Low-Power Fbelp Stop StopGet the latest version from freescale.com Get the latest version from freescale.com Chapter Pins and Connections Device Pin AssignmentPins in bold are added from the next smaller package Pin LqfpRecommended System Connections Basic System Connections Power Reset and RstoOscillator Background / Mode Select BKGD/MS ADC Reference Pins VREFH, Vrefl General-Purpose I/O and Peripheral PortsPriority Pin Assignment by Package and Pin Sharing PriorityPin Number Port Pin AltNumber Port Pin AltGet the latest version from freescale.com Features Chapter Modes of OperationIntroduction MCF51QE128/64/32 Power Modes Conceptual Drawing OverviewCPU / Power Mode Selections PMCFull On Mode Regulator StateStop3 Run Stop2 LPrunTriggers for Transitions Shown in Figure Transition # From TriggerDebug Mode Secure ModeBDM in Low-Power Run Mode Run ModeLow-Power Run Mode LPrun Run ModesBDM in Low-Power Wait Mode Wait ModeLow-Power Wait Mode LPwait Wait ModesStop2 Mode Stop3 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop ModeLow-Range Oscillator Considerations for Stop2 Abbreviations used in Table On-Chip Peripheral Modules in Stop and Low-Power ModesLow-Power Mode Behavior CF1COREICS BDCCOP IRQGet the latest version from freescale.com Get the latest version from freescale.com Kbytes Chapter MemoryMCF51QE128/64/32 Memory Map RAMRead Write Base Address Region Byte CPU Access Type Allowed by RegionRegister Addresses and Bit Assignments Long ByteColdFire Memory Organization Direct-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 2 Register Address NameDirect-Page Register Summary Sheet 3 Direct-Page Register Summary Sheet 4 High-Page Register Summary Sheet 1High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 Reserved Flash Memory Addresses Flash Module Reserved Memory LocationsHigh-Page Register Summary Sheet 5 0x0 0x1 0x2 0x3Reserved Flash Memory Addresses Register 0x0 0x1 0x2 0x3 0x000004080x0000040C NvprotV1 ColdFire Rapid Gpio Memory Map ColdFire Rapid Gpio Memory MapColdFire Interrupt Controller Memory Map V1 ColdFire Interrupt Controller Memory MapIntcsfrc RAMFlash IntccfrcFeatures Lov-Voltage Programming Sequence ExampleAddresses Desired Value Values Programmed Flash Options Register Fopt and Nvopt Register DescriptionsFlash Clock Divider Register Fcdiv Fcdiv Field DescriptionsFlash Configuration Register Fcnfg 10. Fopt Field Descriptions12. Fprot Field Descriptions Flash Protection Register Fprot and Nvprot11. Fcnfg Field Descriptions 13. Flash Protection Address Range0x41 0x00000-0x1EFFF 0x00-0x3F0x40 0x42Fcbef Fccf Fpviol Faccerr Fblank Command buffers are fullFlash Status Register Fstat W1cFunction Description Flash Command OperationsFlash Command Register Fcmd 15. Fcmd Field DescriptionsWriting the Fcdiv Register 200 195 ⎟ 200 = 3%Start Command Write SequenceCommands Impossible ALL Program and Erase16. Flash Command Description Flash CommandsErase Verify Command Fcmd NVMProgram Command 11. Example Program Command Flow Burst Program Command Sequential Sector Erase CommandCommand Buffer Empty Programming13. Example Sector Erase Command Flow Mass Erase Command 14. Example Mass Erase Command FlowFlash Access Violations Illegal Flash OperationsOperating Modes Wait ModeBackground Debug Mode Flash Protection ViolationsUnsecuring the MCU using Backdoor Key Access SecurityReset While Flash Command Active ResetsFlash Reset Sequence Program and Erase TimesSecurity Stop SyncSet PRDIV8 and clock divider fields in CSR3 Device is unsecureChapter Resets, Interrupts, and General System Control Microcontroller ResetControl Bits Clock Source COP Overflow Count COP Configuration OptionsComputer Operating Properly COP Watchdog Copclks CoptPin Configuration Options Illegal Operation ResetIllegal Address Reset Interrupts and ExceptionsEdge and Level Sensitivity Power-On Reset OperationLow-Voltage Detect LVD System External Interrupt InitializationLVD Interrupt Operation LVD Reset OperationPeripheral Clock Gating Low-Voltage Warning LVW Interrupt OperationIrqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack Interrupt Pin Request Status and Control Register IrqscIrqsc Register Field Descriptions IrqpddSystem Reset Status Register SRS PORSystem Options Register 1 SOPT1 POR LVRSystem Options Register 2 SOPT2 SOPT1 Register Field DescriptionsSPI1PS SPSCLK1 MOSI1 MISO1 SS1 System Device Identification Register SDIDH, SdidlSOPT2 Register Field Descriptions IIC1PS SDA1 SCL1Sdidh Register Field Descriptions Sdidl Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack SPMSC1 Register Field Descriptions LPR Lprs Lpwui Ppde Ppdc PpdackSPMSC2 Register Field Descriptions Lvwf 11. LVD and LVW Trip Point Typical Values1Lvwf Lvdv Lvwv Lvwie Lvdvlvwv12. SCGC1 Register Field Descriptions System Clock Gating Control 1 Register SCGC1System Clock Gating Control 2 Register SCGC2 TPM313. SCGC2 Register Field Descriptions RTC SPI2 SPI1FLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Chapter Parallel Input/Output Control Port Data and Data DirectionFreescale Semiconductor 113 Pull-up, Slew Rate, and Drive Strength Port Internal Pull-up EnablePort Slew Rate Enable Data Direction Control Port Data Register Port ReadPort Data Set, Clear and Toggle Data Registers Port Drive Strength SelectFreescale Semiconductor 115 Port Data Set Registers V1 ColdFire Rapid Gpio FunctionalityKeyboard Interrupts Port Data Clear RegistersPull-up/Pull-down Resistors Edge Only SensitivityEdge and Level Sensitivity Freescale Semiconductor 117Keyboard Interrupt Initialization Pin Behavior in Stop ModesParallel I/O, Keyboard Interrupt, and Pin Control Registers Port a RegistersPort a Data Direction Register Ptadd Port a Pull Enable Register PtapePort a Data Register Ptad PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 Port a Slew Rate Enable Register PtasePort a Drive Strength Selection Register Ptads PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0Port B Data Direction Register Ptbdd Port B RegistersPort B Data Register Ptbd Ptads Register Field DescriptionsPtbdd Register Field Descriptions Port B Pull Enable Register PtbpePort B Slew Rate Enable Register Ptbse Ptbpe Register Field DescriptionsPort C Data Register Ptcd Port C RegistersPort B Drive Strength Selection Register Ptbds 10. Ptbds Register Field DescriptionsPort C Data Clear Register Ptcclr Port C Data Direction Register PtcddPort C Data Set Register Ptcset 12. Ptcdd Register Field Descriptions14. Ptcclr Register Field Descriptions Port C Pull Enable Register PtcpePort C Toggle Register Ptctog 16. Ptcpe Register Field DescriptionsPort C Drive Strength Selection Register Ptcds Port C Slew Rate Enable Register PtcsePort D Registers Port D Data Register Ptdd19. Ptdd Register Field Descriptions Port D Pull Enable Register PtdpePort D Data Direction Register Ptddd 20. Ptddd Register Field DescriptionsPort D Drive Strength Selection Register Ptdds Port D Slew Rate Enable Register PtdsePort E Registers Port E Data Register Pted24. Pted Register Field Descriptions Port E Data Direction Register PteddPort E Data Set Register Pteset 25. Ptedd Register Field DescriptionsPort E Toggle Register Ptetog Port E Pull Enable Register PtepePort E Data Clear Register Pteclr PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE029. Ptepe Register Field Descriptions Port E Slew Rate Enable Register PtesePort E Drive Strength Selection Register Pteds 30. Ptese Register Field DescriptionsPort F Data Register Ptfd Port F Pull Enable Register PtfpePort F Registers Port F Data Direction Register Ptfdd34. Ptfpe Register Field Descriptions Port F Slew Rate Enable Register PtfsePort F Drive Strength Selection Register Ptfds 35. Ptfse Register Field DescriptionsPort G Data Direction Register Ptgdd Port G RegistersPort G Data Register Ptgd 36. Ptfds Register Field DescriptionsPort G Drive Strength Selection Register Ptgds Port G Pull Enable Register PtgpePort G Slew Rate Enable Register Ptgse 39. Ptgpe Register Field DescriptionsPort H Data Direction Register Pthdd Port H RegistersPort H Data Register Pthd 41. Ptgds Register Field DescriptionsPort H Drive Strength Selection Register Pthds Port H Pull Enable Register PthpePort H Slew Rate Enable Register Pthse 44. Pthpe Register Field DescriptionsPort J Registers Port J Data Register PtjdPort J Data Direction Register Ptjdd Port J Drive Strength Selection Register Ptjds Port J Pull Enable Register PtjpePort J Slew Rate Enable Register Ptjse 49. Ptjpe Register Field Descriptions51. Ptjds Register Field Descriptions Keyboard Interrupt 1 KBI1 Registers10.1 KBI1 Interrupt Status and Control Register KBI1SC 52. KBI1 Pin MappingKeyboard Interrupt 1 KBI2 Registers 10.2 KBI1 Interrupt Pin Select Register KBI1PE10.3 KBI1 Interrupt Edge Select Register KBI1ES 57. KBI2SC Register Field Descriptions 11.1 KBI2 Interrupt Status and Control Register KBI2SC11.2 KBI2 Interrupt Pin Select Register KBI2PE 58. KBI2PE Register Field Descriptions11.3 KBI2 Interrupt Edge Select Register KBI2ES 59. KBI2ES Register Field DescriptionsFreescale Semiconductor 143 144 Freescale Semiconductor Chapter ColdFire Core OverviewMemory Map/Register Description Data Registers D0-D7 Supervisor/User Access RegistersSupervisor Access Only Registers ColdFire Core Programming ModelAddress Registers A0-A6 Supervisor/User Stack Pointers A7 and OTHERA7Data Condition Code Register CCR Freescale Semiconductor 149Program Counter PC Vector Base Register VBRCCR Field Descriptions CPU Configuration Register Cpucr Status Register SR SR Field DescriptionsBWD Instruction Enhancements over Revision Isaa Functional DescriptionInstruction Set Architecture Isac Instruction DescriptionException Processing Overview Exception Vector Assignments Vector StackedAssignment Numbers Offset Hex Counter Numbers Offset Hex Counter Exception Stack Frame DefinitionAssignment SSP →Format Field Encodings Fault Status Encodings2.2 S08 and ColdFire Exception Processing Comparison FS30 DefinitionException Processing Comparison Attribute S08 V1 ColdFireRTI RTE Processor Exceptions Access Error ExceptionAddress Error Exception Freescale Semiconductor 159Line OpMode Effective Address Illegal Instruction Exception10. ColdFire Opword Line Definition OpwordLine Instruction ClassPrivilege Violation Trace ExceptionFreescale Semiconductor 161 Unimplemented Line-F Opcode RTE and Format Error ExceptionUnimplemented Line-A Opcode Debug InterruptUnsupported Instruction Exception Fault-on-Fault HaltTrap Instruction Exception Interrupt ExceptionBDM Load 0x60 D0 Store 0x40 D0 Reset ExceptionAccess User read-only BDM read-only VER REV11. D0 Hardware Configuration Info Field Description 12. D1 Hardware Configuration Information Field Description FlashszSramsz 13. Misaligned Operand References Instruction Execution TimingTiming Assumptions Address10 Size Bus Additional Operations CR/W15. Move Long Execution Times Move Instruction Execution Times14. Move Byte and Word Execution Times Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wlStandard One Operand Instruction Execution Times 16. One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Standard Two Operand Instruction Execution Times 17. Two Operand Instruction Execution TimesMiscellaneous Instruction Execution Times 18. Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Branch Instruction Execution Times 19. General Branch Instruction Execution Times20. Bcc Instruction Execution Times Chapter Interrupt Controller CF1INTC AttributeHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x150 Next SCI2rx 0x154 SCI2tx 0x158 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x1440x148 Next ACMPx 0x14C 0x180 NextInterrupt Source Number To V1 ColdFire coreFreescale Semiconductor 177 External Signal Description Memory Map and Register DefinitionModes of Operation Memory Map Intc Force Interrupt Register IntcfrcCF1INTC Memory Map Intcfrc Field Descriptions Intc Wake-up Control Register Intcwcr INTCPL6P7,6 Field DescriptionsFreescale Semiconductor 181 Intc Set Interrupt Force Register Intcsfrc Intcwcr Field DescriptionsENB Intccfrc Field Descriptions Intc Clear Interrupt Force Register IntccfrcIntcsfrc Field Descriptions Offset CF1INTCBASE + 0x1F IntccfrcIntc Software and Level-nIACK Registers n = 1,2,3,...,7 Vecn Swiack10. Legend for Table Interrupt Request Level and Priority AssignmentsINTCSWIACK, INTCLVLnIACK Field Descriptions Priority within Level Midpoint12. V1 ColdFire Interrupt Assignments TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovflTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Initialization Information Application InformationEmulation of the HCS08’s 1-Level IRQ Handling Using INTCPL6P7,6 Registers More on Software IACKsFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Chapter Rapid Gpio Rgpio Freescale Semiconductor 193V1 ColdFire Core Freescale Semiconductor 195 OEP Dsoc IFPCore RAM RgpioPin Muxing + Pad Logic On-platform Bus RgpioModule RGPIODATA150Detailed Signal Descriptions Rgpio Module External I/O SignalsRgpio Detailed Signal Descriptions Memory Map/Register Definition Rgpio Write Memory MapRgpio Read Memory Map Rgpiodir Field Descriptions Rgpio Data Direction RgpiodirRgpio Data Rgpiodata DIRRgpio Pin Enable Rgpioenb Rgpio Clear Data RgpioclrRgpioclr Field Descriptions Rgpio Set Data RgpiosetRgpio Toggle Data Rgpiotog Rgpioset Field DescriptionsTOG Application 1 Simple Square-Wave Generation10. Rgpiotog Field Descriptions Field Description 15-0 Rgpio Toggle Data11. Square-Wave Output Performance 29x 12. Emulated SPI Performance using Gpio OutputsSPI Speed @ Relative CPU f = 50 MHz Freescale Semiconductor 205206 Freescale Semiconductor Chapter Analog Comparator 3V ACMPVLPV1 Acmp Configuration InformationACMP/TPM Configuration Information Acmp Clock GatingInterrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Stop3 Mode Operation Block DiagramWait Mode Operation Stop2 Mode OperationAcbgs Acpe Register DefinitionStatus and Control Register ACMPxSC Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACFAcme InterruptsACMPxSC Field Descriptions Acmod214 Freescale Semiconductor Chapter Analog-to-Digital Converter S08ADC12V1 ADC Clock GatingFreescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 Alternate Clock Module ConfigurationsChannel Assignments ADC Channel AssignmentTemperature Sensor Hardware Trigger2provides a block diagram of the ADC module Freescale Semiconductor 219Signal Properties Name FunctionAD27-AD0 Voltage Reference High Vrefh Analog Power VddadAnalog Ground Vssad Voltage Reference Low VreflCoco Input Channel SelectInput Select ADCSC2 Register Field Descriptions Status and Control Register 2 ADCSC2Data Result High Register Adcrh AdactADR10 ADR9 ADR8 Data Result Low Register AdcrlCompare Value High Register Adccvh ADCV11 ADCV10 ADCV9 ADCV8Adccfg Register Field Descriptions Configuration Register AdccfgCompare Value Low Register Adccvl AdlpcConversion Modes Pin Control 1 Register APCTL1Clock Divide Select Input Clock SelectPin Control 2 Register APCTL2 10. APCTL1 Register Field DescriptionsADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 ADPC15 Pin Control 3 Register APCTL311. APCTL2 Register Field Descriptions ADPC23ADPC20 12. APCTL3 Register Field DescriptionsADPC21 ADPC16Hardware Trigger Clock Select and Divide ControlInput Select and Pin Control Conversion ControlAborting Conversions Initiating ConversionsCompleting Conversions Freescale Semiconductor 23113. Total Conversion Time vs. Control Conditions Power ControlSample Time and Total Conversion Time Adiclk AdlsmpMCU Wait Mode Operation Automatic Compare FunctionStop3 Mode With Adack Disabled MCU Stop3 Mode OperationMCU Stop2 Mode Operation Stop3 Mode With Adack EnabledPseudo-Code Example ADC Module Initialization ExampleInitialization Sequence Freescale Semiconductor 235COCO=1? External Pins and RoutingReset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No Yes Read Adcrh Then Adcrl To Clear Coco Bit ContinueAnalog Input Pins Analog Supply PinsAnalog Reference Pins Freescale Semiconductor 237Pin Leakage Error Sources of ErrorSampling Error Noise-Induced ErrorsLsb = Code Width and Quantization ErrorLinearity Errors Freescale Semiconductor 239Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor External Oscillator Stop2 Mode ConsiderationsChapter Internal Clock Source S08ICSV3 Freescale Semiconductor 243Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor HGO, RANGE, EREFS, ERCLKEN, Erefsten Freescale Semiconductor 2472is the ICS block diagram ICS Register Summary FLL Bypassed Internal Low Power FbilpFLL Bypassed External Low Power Fbelp Rdiv IrefsClks Rdiv Irefs Irclken Irefsten ICS Control Register 1 ICSC1ICSC1 Field Descriptions Reference Divide FactorICSC2 Field Descriptions ICS Control Register 2 ICSC2ICS Trim Register Icstrm Bdiv Range HGO Erefs Erclken ErefstenIcssc Field Descriptions ICS Status and Control IcsscIcstrm Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRS608 19.92 MHz Reference range FLL factor DCO range512 16 20 MHz 1024 32 40 MHzIREFS=1 CLKS=00 IREFS=0 Operational ModesFLL Engaged Internal FEI IREFS=0 CLKS=10FLL Bypassed Internal FBI FLL Bypassed Internal Low Power FbilpFLL Engaged External FEE FLL Bypassed External FBEBus Frequency Divider Mode SwitchingFLL Bypassed External Low Power Fbelp StopInternal Reference Clock Low Power Bit UsageDCO Maximum Frequency with 32.768 kHz Oscillator External Reference ClockFixed Frequency Clock Local ClockIIC1 Position Options Module ConfigurationChapter Inter-Integrated Circuit S08IICV2 SOPT2IIC1PSMCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SCL Serial Clock Line SDA Serial Data LineFreescale Semiconductor 263 Iica Field Descriptions IIC Address Register IicaIIC Frequency Divider Register Iicf = Unimplemented or ReservedHold Times μs Iicf Field DescriptionsHold Time Values for 8 MHz Bus Speed Mult ICR SDAIIC Divider and Hold Values ICR SCLIIC Control Register IICC1 IICC1 Field DescriptionsIIC Status Register Iics Iics Field DescriptionsTCF Iicd Field Descriptions IIC Data I/O Register IicdIIC Control Register 2 IICC2 Freescale Semiconductor 269IIC Protocol IICC2 Field DescriptionsGcaen Start Signal Slave Address TransmissionFreescale Semiconductor 271 Arbitration Procedure Stop SignalRepeated Start Signal Data TransferClock Stretching Clock SynchronizationHandshaking Freescale Semiconductor 27313.4.2 10-bit Address Master-Transmitter Addresses a Slave-ReceiverMaster-Receiver Addresses a Slave-Transmitter Byte Transfer Interrupt ResetsGeneral Call Address Address Detect Interrupt276 Freescale Semiconductor Module Initialization Master Initialization/Application InformationModule Initialization Slave Module Use12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor RTC Clock Sources Chapter Real-Time Counter S08RTCV1ADC Hardware Trigger RTC Modes of OperationInterrupt Vector MCF51QE128 Block Diagram Highlighting RTC Block and Pins Freescale Semiconductor 283Active Background Mode Erclk RTC Register SummaryLPO IrclkRTC Prescaler Divide-by values RTC Status and Control Register RtcscRtcsc Field Descriptions RtifRtccnt Field Descriptions RTC Counter Register RtccntRTC Modulo Register Rtcmod Rtcmod Field DescriptionsRtcps RTC Operation ExamplePrescaler Period KHz Internal Clock MHz External Clock Rtclks =0x52 0x53 0x54 0x55 0x00 0x01 Internal 1-kHz Clock Source RTC Clock Rtcps =Rtccnt Rtif Freescale Semiconductor 289290 Freescale Semiconductor Chapter Serial Communications Interface S08SCIV4 SCI Clock GatingFreescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI SCI Receiver Block Diagram Freescale Semiconductor 297SCI Baud Rate Registers SCIxBDH, SCIxBDL SCIxBDH Field DescriptionsLbkdie Loops Sciswai Rsrc Wake ILT SCI Control Register 1 SCIxC1SCIxBDL Field Descriptions LoopsSCI Control Register 2 SCIxC2 SCIxC2 Field DescriptionsTIE SCI Status Register 1 SCIxS1 Tdre Rdrf IdleParity error Framing errorNo parity error SCIxDLbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF SCI Status Register 2 SCIxS2SCIxS2 Field Descriptions RXINV1Txdir SCI Control Register 3 SCIxC3SCIxC3 Field Descriptions TXINV1SCI Data Register SCIxD Baud Rate GenerationFreescale Semiconductor 305 Transmitter Functional Description Send Break and Queued IdleBreak Character Length Receiver Functional DescriptionData Sampling Technique BRK13Receiver Wakeup Operation Idle-Line WakeupInterrupts and Status Flags Freescale Semiconductor 309Additional SCI Functions Stop Mode OperationLoop Mode 15.3.5.1 8- and 9-Bit Data ModesSingle-Wire Operation Freescale Semiconductor 311312 Freescale Semiconductor Chapter Serial Peripheral Interface S08SPIV3 SPI Clock GatingFreescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor Block Diagrams SPI System Block DiagramFreescale Semiconductor 317 SPI Module Block Diagram SPI Baud Rate Generation Freescale Semiconductor 319Miso Master Data In, Slave Data Out Spsck SPI Serial ClockMosi Master Data Out, Slave Data SS Slave SelectSPI Control Register 1 SPIxC1 Modes of OperationSPI in Stop Modes SPIxC1 Field DescriptionsSS Pin Function Master Mode Slave ModeSPI Control Register 2 SPIxC2 Modfen SsoeSPIxC2 Register Field Descriptions SPI Stop in Wait ModeSPI Baud Rate Register SPIxBR Modfen Bidiroe SpiswaiSppr SPI Status Register SPIxSSPIxBR Register Field Descriptions SPRSPI Data Register SPIxD SPI Clock Formats 10. SPI Clock Formats Cpha = Freescale Semiconductor 327SPI Interrupts 11. SPI Clock Formats Cpha =Mode Fault Detection Freescale Semiconductor 329330 Freescale Semiconductor Chapter Timer/Pulse-Width Modulator S08TPMV3 TPM Clock GatingFreescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor TPM Block Diagram Freescale Semiconductor 337Signal Description ExtclkTPMxCHn TPM Channel n I/O Pins Extclk External Clock SourceFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TOF Toie Cpwms Clksb Clksa PS2 PS1 TPM Status and Control Register TPMxSCTPMxSC Field Descriptions TOFPrescale Factor Selection TPM Counter Registers TPMxCNTHTPMxCNTLTPM-Clock-Source Selection ClksbclksaTPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter TPM Counter Modulo Registers TPMxMODHTPMxMODLTPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter Freescale Semiconductor 343TPMxMOD70 TPM Channel n Status and Control Register TPMxCnSCTPMxMOD158 CHnF CHnIE MSnB MSnA ELSnB ELSnAMode, Edge, and Level Selection MSnBMSnA ELSnBELSnA Mode ConfigurationTPMxCnSC Field Descriptions CpwmsTPMxCnV158 TPM Channel Value Registers TPMxCnVHTPMxCnVLMode, Edge, and Level Selection TPMxCnV70Counter Counter Clock SourceFreescale Semiconductor 347 Counter Overflow and Modulo Reset TPM Clock Source SelectionInput Capture Mode Channel Mode SelectionManual Counter Reset Output Compare ModeEdge-Aligned PWM Mode 15. PWM Period and Pulse Width ELSnA=0Center-Aligned PWM Mode Freescale Semiconductor 351Reset Overview Description of Reset OperationGeneral Description of Interrupt Operation Timer Overflow Interrupt TOF DescriptionInterrupt Local Source Description Enable Interrupt SummaryChannel Event Interrupt Description Center-Aligned PWM CaseChapter Version 1 ColdFire Debug CF1DEBUG Freescale Semiconductor 355PST Version 1 ColdFire Core CF1CoreOEP Bkgd BDCRevision Modes of OperationsDebug Revision Summary Csrhrl CSR2D1HRLCore Status Command Set BDM Command TypesCommand Type Flash BDM?External Signal Descriptions Debug Module Signals DescriptionBDM GO DRc Register Name Width Access Reset Value Section Bits Debug Module Memory MapCPU Configuration/Status Register CSR CSR Field Descriptions Bstat FOF TRG Halt Bkpt HRL BKD IPWTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Extended Configuration/Status Register Xcsr Xcsr Reference SummaryMethod Reference Details Xcsr CPU Cstat Halt Stop Eseqc Clksw SEC Erase EnbdmApcsc Apce CPU StateEseqc W SEC RErase W Xcsr CSR2 Configuration/Status Register 2 CSR2CSR2 Reference Summary Syncpc IntervalCSR2 Field Descriptions PSTBWA7 Pstb Valid Data Locations Oldest to NewestPstbss Configuration/Status Register 3 CSR310. CSR3 Reference Summary Start Condition Stop ConditionBDM Address Attribute Register Baar BFC Bfcdiv DIV8BFCDIV8 Address Attribute Trigger Register Aatr SZM TTM TMMTrigger Definition Register TDR Signal of the processor’s local busBDM memory commands Normal processor access Else Reserved SZML2T L1T L2EDL2EA L1EAL2T Three bits disables the address breakpoint Program Counter Breakpoint/Mask Registers PBR0-3, PbmrNo inversion Invert data breakpoint comparators DRc 0x08 PBR0 Mask Reset15. PBR0 Field Descriptions DRc 0x09 PbmrAbhr Address Breakpoint Registers ABLR, Abhr17. Pbmr Field Descriptions AblrData Breakpoint and Mask Registers DBR, Dbmr 19. Abhr Field Description21. Dbmr Field Descriptions Address1 Access Size Operand Location Background Debug Mode BDM22. Access Size and Operand Data Location Resulting Set of Possible Trigger CombinationsHalt Source Halt Timing Description CPU Halt23. CPU Halt Sources Cpucrard =Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details 15. BDC Host-to-Target Serial Bit Timing Freescale Semiconductor 38516. BDC Target-to-Host Serial Bit Timing Logic BDM Command Set Descriptions Freescale Semiconductor 387Core Register Commands Miscellaneous CommandsMemory Commands PST Trace Buffer Read CommandsCRG CRN 24. BDM Command Code Field DescriptionsCRG VBRAckdisable BDM Command Set Summary25. BDM Command Summary AckenableReadcreg ReaddregReadpstb Syncpc Writecreg0x03 Disable host/target handshake protocol Always AvailableEnable host/target handshake protocol Always Available Freescale Semiconductor 393Data7-0 Enter active background mode if enabled Non-intrusive0x32 Host → Target Memory data7-0 Target → 0x36 0x3A Memory0x37 0x33Xcsrsb 0x3B0x12 Memory 0x12 Memory data7-0Target 0x16 Memory Data15-8 Memory data7-0 Target → Host 0x16 MemoryNo operation Non-intrusive Read CPU control register Active Background0x30 Address23-0 Read debug control register Non-intrusive0xA0+CRN Host → Target Dreg data Target Memory data7-0 Target → Host0x39 0x310x35 0x50+CRN Host → Target Pstb dataRead CSR2 Status Byte Always Available Read general-purpose CPU register Active BackgroundRead Xcsr Status Byte Always Available Read CSR3 Status Byte Always Available0xC0+CRN Creg data Synchronize PC to PST/DDATA Signals Non-intrusiveWrite CPU control register Active Background Freescale Semiconductor 4010x10 Address23-0 Memory Data7-0 Write debug control register Non-intrusive0x80+CRN Dreg data Host → targetWrite general-purpose CPU register Active Background Write CSR2 Status Byte Always Available Serial Interface Hardware Handshake ProtocolWrite Xcsr Status Byte Always Available Write CSR3 Status Byte Always Available19. Target Acknowledge Pulse ACK Freescale Semiconductor 405Hardware Handshake Abort Procedure 20. Handshake Protocol at Command Level21signal timing is not drawn to scale Freescale Semiconductor 40721. ACK Abort Procedure at the Command Level Real-Time Debug Support Real-Time Trace SupportFreescale Semiconductor 409 PST40 Definition Enter user mode26. Processor Status Encodings Instructions, generate different encodingsBegin Execution of Taken Branch PST = 0x08-0x0BFreescale Semiconductor 411 23. Example JMP Instruction Output in Pstb PST Values DescriptionPstbpst PST Trace Buffer Pstb18.4.3.3 PST/DDATA Example PstbddataProcessor Status, Debug Data Definition PST/DDATA 27. PST/DDATA Specification for User-Mode InstructionsInstruction Operand Syntax Freescale Semiconductor 415416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set No Connect GND ResetFreescale-Recommended BDM Pinout Freescale Semiconductor 419420 Freescale Semiconductor MCF51QE128RM Rev to Rev Changes Appendix a Revision HistoryChanges between Rev and Rev Chapter DescriptionRevision History Page How to Reach Us