Chapter 8 Interrupt Controller (CF1_INTC)

The interrupt controller's wake-up signal is defined as:

wake-up = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK])

Reset state of the INTC_WCR is disabled, so this register must be written to enable the wake-up condition before the core executes any STOP instructions.

Offset: CF1_INTC_BASE + 0x1B (INTC_WCR)

Access: Read/Write

R

W Reset

7

6

5

4

3

2

1

0

ENB

0

0

0

0

 

MASK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

Figure 8-4. INTC_WCR Register

 

Table 8-6. INTC_WCR Field Descriptions

 

 

Field

Description

 

 

7

Enable.

ENB

0 Wake-up signal disabled.

 

1 Enables the assertion of the combinational wake-up signal to the clock generation logic.

 

 

6–3

Reserved, must be cleared.

 

 

2–0

Interrupt mask level. Defines the interrupt mask level during wait or stop mode and is enforced by the hardware to

MASK

be within the range 0–6. If INTC_WCR[ENB] is set, after an interrupt request of a level higher than MASK is asserted,

 

the wake-up signal to the clock generation logic is asserted.

 

 

8.3.2.4INTC Set Interrupt Force Register (INTC_SFRC)

The INTC_SFRC register provides a simple memory-mapped mechanism to set a given bit in the INTC_FRC register to assert a specific level interrupt request. The data value written causes the appropriate bit in the INTC_FRC register to be set. Attempted reads of this register generate an error termination.

This register is provided so interrupt service routines can generate a forced interrupt request without the need to perform a read-modify-write sequence on the INTC_FRC register.

Offset: CF1_INTC_BASE + 0x1E (INTC_SFRC)

Access: Write-only

R

W Reset

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

0

0

 

 

 

SET

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

Figure 8-5. INTC_SFRC Register

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual Intc Set Interrupt Force Register Intcsfrc, Intcwcr Field Descriptions, Enb