Freescale Semiconductor MCF51QE128RM manual CPU Configuration Register Cpucr

	ColdFire Core
BDM: 0x801 (VBR)	Access: Supervisor read/write
Load: 0xE1 (VBR)	BDM read/write
Store: 0xC1 (VBR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7 6 5 4

3 2 1 0

R	0	0	0	0	0	0	0	0		Base			0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
W										Address
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 7-7. Vector Base Register (VBR)

7.2.7CPU Configuration Register (CPUCR)

The CPUCR provides supervisor mode configurability of specific core functionality. Certain hardware features can be enabled/disabled individually based on the state of the CPUCR.

BDM: 0x802 (CPUCR)	Access: Supervisor read/write
Load: 0xE2 (CPUCR)	BDM read/write
Store: 0xC2 (CPUCR)

31 30 29 28

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7 6 5 4

3 2 1 0

R

W

ARD IRD IAE IME BWD

0

FSD

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

0 0 0 0 0

0 0 0 0 0

Reset 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

		Figure 8. CPU Configuration Register (CPUCR)
		Table 3. CPUCR Field Descriptions
Field		Description
31	Address-related reset disable. Used to disable the generation of a reset event in response to a processor exception
ARD	caused by an address error, a bus error, an RTE format error, or a fault-on-fault halt condition.
	0	The detection of these types of exception conditions or the fault-on-fault halt condition generate a reset event.
	1	No reset is generated in response to these exception conditions.
30	Instruction-related reset disable. Used to disable the generation of a reset event in response to a processor exception
IRD	caused by the attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal
	line F instructions, or a privilege violation.
	0	The detection of these types of exception conditions generate a reset event.
	1	No reset is generated in response to these exception conditions.
29	Interrupt acknowledge (IACK) enable. Forces the processor to generate an IACK read cycle from the interrupt
IAE	controller during exception processing to retrieve the vector number of the interrupt request being acknowledged. The
	processor’s execution time for an interrupt exception is slightly improved when this bit is cleared.
	0	The processor uses the vector number provided by the interrupt controller at the time the request is signaled.
	1	IACK read cycle from the interrupt controller is generated.
28	Interrupt mask enable. Forces the processor to raise the interrupt level mask (SR[I]) to 7 during every
IME	interrupt exception. This capability is provided to assist when porting S08 application code to ColdFire.
	0	As part of an interrupt exception, the processor sets SR[I] to the level of the interrupt being serviced.
	1	As part of an interrupt exception, the processor sets SR[I] to 7. This disables all level 1-6 interrupt requests but
		allows recognition of the edge-sensitive level 7 requests.
		MCF51QE128 MCU Series Reference Manual, Rev. 3
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