Freescale Semiconductor MCF51QE128RM manual System Clock Gating Control 1 Register SCGC1, TPM3

Chapter 5 Resets, Interrupts, and General System Control

5.7.9System Clock Gating Control 1 Register (SCGC1)

This high page register contains control bits to enable or disable the bus clock to the TPMx, ADC, IICx, and SCIx modules. Gating off the clocks to unused peripherals reduces the MCU’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,” for more information.

R

W

Reset:

7	6	5	4	3	2	1	0
TPM3	TPM2	TPM1	ADC	IIC2	IIC1	SCI2	SCI1
1	1	1	1	1	1	1	1

		Figure 5-10. System Clock Gating Control 1 Register (SCGC1)
		Table 5-12. SCGC1 Register Field Descriptions
Field		Description
7	TPM3 Clock Gate Control. This bit controls the clock gate to the TPM3 module.
TPM3	0	Bus clock to the TPM3 module is disabled.
	1	Bus clock to the TPM3 module is enabled.
6	TPM2 Clock Gate Control. This bit controls the clock gate to the TPM2 module.
TPM2	0	Bus clock to the TPM2 module is disabled.
	1	Bus clock to the TPM2 module is enabled.
5	TPM1 Clock Gate Control. This bit controls the clock gate to the TPM1 module.
TPM1	0	Bus clock to the TPM1 module is disabled.
	1	Bus clock to the TPM1 module is enabled.
4	ADC Clock Gate Control. This bit controls the clock gate to the ADC module.
ADC	0	Bus clock to the ADC module is disabled.
	1	Bus clock to the ADC module is enabled.
3	IIC2 Clock Gate Control. This bit controls the clock gate to the IIC2 module.
IIC2	0	Bus clock to the IIC2 module is disabled.
	1	Bus clock to the IIC2 module is enabled.
2	IIC1 Clock Gate Control. This bit controls the clock gate to the IIC1 module.
IIC1	0	Bus clock to the IIC1 module is disabled.
	1	Bus clock to the IIC1 module is enabled.
1	SCI2 Clock Gate Control. This bit controls the clock gate to the SCI2 module.
SCI2	0	Bus clock to the SCI2 module is disabled.
	1	Bus clock to the SCI2 module is enabled.
0	SCI1 Clock Gate Control. This bit controls the clock gate to the SCI1 module.
SCI1	0	Bus clock to the SCI1 module is disabled.
	1	Bus clock to the SCI1 module is enabled.

5.7.10System Clock Gating Control 2 Register (SCGC2)

This high page register contains control bits to enable or disable the bus clock to the IRQ, KBI, ACMP, RTC, and SPIx modules. Gating off the clocks to unused peripherals reduces the MCU’s run and wait currents. See Section 5.6, “Peripheral Clock Gating,” for more information.

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 107

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