Freescale Semiconductor MCF51QE128RM Write debug control register Non-intrusive, Host → target

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

18.4.1.5.19 WRITE_DREG

Write debug control register Non-intrusive

0x80+CRN

DREG data	DREG data	DREG data	DREG data
[31–24]	[23–16]	[15–8]	[7–0]

host →	host →	host →	host →	host →	D
target	target	target	target	target	L
					Y

This command writes the 32-bit operand to the selected debug control register. This grouping includes all the debug control registers ({X}CSRn, BAAR, AATR, TDR, PBRn, PBMR, ABxR, DBR, DBMR). Accesses to debug control registers are always 32-bits wide, regardless of implemented register width. The register is addressed through the core register number (CRN). See Table 18-4for CRN details.

18.4.1.5.20 WRITE_MEM.sz, WRITE_MEM.sz_WS

WRITE_MEM.sz

Write memory at the specified address Non-intrusive

0x10

Address[23-0]

Memory

data[7–0]

host →	host → target	host →	D
target		target	L
			Y

0x14

Address[23-0]

Memory

data[15–8]

Memory

data[7–0]

host →	host → target	host →	host →	D
target		target	target	L
				Y

0x18

Address[23-0]

Memory

data[31–24]

Memory

data[23–16]

Memory

data[15–8]

Memory

data[7–0]

host →	host → target	host →	host →	host →	host →	D
target		target	target	target	target	L
						Y

MCF51QE128 MCU Series Reference Manual, Rev. 3

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