Chapter 3 Modes of Operation

Table 3-2. Triggers for Transitions Shown in Figure 3-2(continued)

Transition #

From

To

Trigger

 

 

 

 

 

Stop3

Run

Interrupt when LPWUI=1

8

 

 

 

Run

Stop3

Pre-configure settings shown in Table 3-1, execute

 

 

STOP instruction

 

 

 

 

 

 

 

 

 

 

When a BACKGROUND command is received

9

Stop4

Halt

through the BKGD/MS pin (ENBDM must equal

 

 

one).

 

 

 

 

 

Halt

Stop4

Not supported.

 

 

 

 

 

Halt

Run

GO instruction issued via BDM

 

 

 

 

10

 

 

When a BACKGROUND command is received

Run

Halt

through the BKGD/MS pin OR

 

 

When a HALT instruction is executed OR

 

 

 

 

 

 

When encountering a BDM breakpoint

 

 

 

 

 

 

 

When a BACKGROUND command is received

11

Wait

Halt

through the BKGD/MS pin (ENBDM must equal

 

 

one).

 

 

 

 

 

Halt

Wait

Not supported.

 

 

 

 

1An analog connection from this pin to the on-chip regulator wakes up the regulator, which then initiates a power-on-reset sequence.

Individual power states are discussed in more detail in the following sections.

3.4Debug Mode

Debug mode functions are managed through the background debug controller (BDC) in the Version 1 ColdFire core. The BDC provides the means for analyzing MCU operation during software development.

The debug interface is used to program a bootloader or user application program into the flash program memory before the MCU is operated in run mode for the first time. When the MCF51QE128/64/32 is shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted, so there is no program that could be executed in run mode until the flash memory is initially programmed. The debug interface can also be used to erase and reprogram the flash memory after it has been previously programmed.

See Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for more details regarding the debug interface.

3.5Secure Mode

While the MCU is in secure mode, there are severe restrictions on which debug commands can be used. In this mode, only the upper byte of the core’s XCSR, CSR2, and CSR3 registers can be accessed. See Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for details.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual Debug Mode, Secure Mode