Freescale Semiconductor MCF51QE128RM manual SPI Status Register SPIxS, Sppr, Spr

	Table 16-4. SPIxBR Register Field Descriptions
Field			Description
7	Reserved, should be cleared.
6–4	SPI Baud Rate Prescale Divisor. This 3-bit field selects one of eight divisors for the SPI baud rate prescaler as
SPPR	shown below. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the
	input of the SPI baud rate divider (see Figure 16-4).
		SPPR	Prescaler Divisor	SPPR	Prescaler Divisor
		000	1	100	5
		001	2	101	6
		010	3	110	7
		011	4	111	8
3	Reserved, should be cleared.
2–0	SPI Baud Rate Divisor. This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown below.
SPR	The SPI baud rate prescaler supplies the input to this divider (see Figure 16-4). The output of this divider is the
	SPI bit rate clock for master mode.
		SPR	Rate Divisor	SPR	Rate Divisor
		000	2	100	32
		001	4	101	64
		010	8	110	128
		011	16	111	256

16.4.4SPI Status Register (SPIxS)

This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not reserved and always read 0. Writes have no meaning or effect.

R

W

Reset

7	6	5	4	3	2	1	0
SPRF	0	SPTEF	MODF	0	0	0	0
0	0	1	0	0	0	0	0

Figure 16-8. SPI Status Register (SPIxS)

	Table 16-5. SPIxS Register Field Descriptions
Field	Description
7	SPI Read Buffer Full Flag. SPRF is set at the completion of an SPI transfer to indicate that received data may be
SPRF	read from the SPI data register (SPIxD). SPRF is cleared by reading SPRF while it is set, then reading SPIxD.
	0 No data available in the receive data buffer
	1 Data available in the receive data buffer
6	Reserved, should be cleared.
	MCF51QE128 MCU Series Reference Manual, Rev. 3
324	Freescale Semiconductor
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