Freescale Semiconductor MCF51QE128RM manual Description of Interrupt Operation, Interrupt Summary

Timer/PWM Module (S08TPMV3)

All TPM interrupts are listed in Table 17-8, showing the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic.

Table 17-8. Interrupt Summary

Interrupt	Local	Source	Description
	Enable
			Set each time the timer counter reaches its terminal
TOF	TOIE	Counter overflow	count (at transition to next count value which is
			usually 0x0000)
CHnF	CHnIE	Channel event	An input capture or output compare event took
			place on channel n

The TPM module provides a high-true interrupt signal. Vectors and priorities are determined at chip integration time in the interrupt module. Refer to the interrupt chapter for details.

17.6.2Description of Interrupt Operation

For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt generates when the associated interrupt flag is set. Software must perform a sequence of steps to clear the interrupt flag before returning from the interrupt service routine.

TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set followed by a write of zero to the bit. If a new event is detected between these two steps, the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event.

17.6.2.1Timer Overflow Interrupt (TOF) Description

The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system (general purpose timing functions versus center-aligned PWM operation). The flag is cleared by the two step sequence described above.

17.6.2.1.1Normal Case

Normally, TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not configured for center-aligned PWM (CPWMS = 0), TOF is set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning of counter overflow.

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 353

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