Freescale Semiconductor MCF51QE128RM manual Address Attribute Trigger Register Aatr, Szm Ttm Tmm

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

DRc: 0x05 (BAAR)	Access: Supervisor write-only
	BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7 6 5 4

3 2 1 0

	R
	W	0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	R	SZ		TT			TM
Reset		0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1
								Figure 18-7. BDM Address Attribute Register (BAAR)
											Table 18-12. BAAR Field Descriptions
Field																	Description
31–8	Reserved for future use by the debug module, must be cleared.
7	Read/Write.
R	0	Write
	1 Read
6–5	Size.
SZ	00	Longword
	01	Byte
	10	Word
	11	Reserved
4–3	Transfer type. See the TT definition in the AATR description, Section 18.3.6, “Address Attribute Trigger Register
TT	(AATR)”.
2–0	Transfer modifier. See the TM definition in the AATR description, Section 18.3.6, “Address Attribute Trigger Register
TM	(AATR)”.

18.3.6Address Attribute Trigger Register (AATR)

AATR defines address attributes and a mask to be matched in the trigger. The register value is compared with address attribute signals from the processor’s high-speed local bus, as defined by the setting of the trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WRITE_DREG command.

DRc: 0x06 (AATR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

Access: Supervisor write-only BDM write-only

7 6 5 4 3 2 1 0

R
W	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	RM	SZM		TTM			TMM		R	SZ		TT			TM
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1
							Figure 18-8. Address Attribute Trigger Register (AATR)
										Table 18-13. AATR Field Descriptions
Field																	Description
31–16 Reserved, must be cleared.

15Read/write mask. Masks the R bit in address comparisons.

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MCF51QE128 MCU Series Reference Manual, Rev. 3

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