Freescale Semiconductor MCF51QE128RM manual Iicf Field Descriptions, Hold Times μs, Mult ICR SDA

	Table 13-3. IICF Field Descriptions
Field	Description
7–6	IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider,
MULT	generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
	00 mul = 01
	01 mul = 02
	10 mul = 04
	11 Reserved
5–0	IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
ICR	bits determine the IIC baud rate, the SDA hold time, the SCL Start hold time, and the SCL Stop hold time.
	Table 13-5provides the SCL divider and hold values for corresponding values of the ICR.
	The SCL divider multiplied by multiplier factor mul generates IIC baud rate.
	bus speed (Hz)	Eqn. 13-1
	IIC baud rate = --------------------------------------------
	mul ⋅ SCLdivider
	SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
	SDA hold time = bus period (s) ⋅ mul ⋅ SDA hold value	Eqn. 13-2
	SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
	falling edge of SCL (IIC clock).
	SCL Start hold time = bus period (s) ⋅ mul ⋅ SCL Start hold value	Eqn. 13-3
	SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
	SDA (IIC data) while SCL is high (Stop condition).
	SCL Stop hold time = bus period (s) ⋅ mul ⋅ SCL Stop hold value	Eqn. 13-4

For example, if the bus speed is 8 MHz, the table below shows the possible hold time values with different ICR and MULT selections to achieve an IIC baud rate of 100kbps.

Table 13-4. Hold Time Values for 8 MHz Bus Speed

			Hold Times (μs)
MULT	ICR
		SDA	SCL Start	SCL Stop
0x2	0x00	3.500	4.750	5.125
0x1	0x07	2.500	4.250	5.125
0x1	0x0B	2.250	4.000	5.250
0x0	0x14	2.125	4.000	5.250
0x0	0x18	1.125	3.000	5.500

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 2-265