Freescale Semiconductor MCF51QE128RM manual 0x12 Memory data7-0, Target → Host 0x16 Memory

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

0x12

Memory data[7-0]

host →	host →	D
target	target	L
		Y

0x16

Memory

data[15-8]

Memory data[7-0]

host →	host →	host →	D
target	target	target	L
			Y

0x1A

Memory

data[31-24]

Memory

data[23-16]

Memory

data[15-8]

Memory data[7-0]

host →	host →	host →	host →	host →	D
target	target	target	target	target	L
					Y
		FILL_MEM.sz_WS
Write memory specified by debug address register with					Non-intrusive
status, then increment address

0x12	Memory
	data[7-0]

host →	host →
target	target

XCSR_SB

Dtarget →

L

Y host

0x16	Memory	Memory		XCSR_SB
	data[15-8]	data[7-0]
host →	host →	host →	D	target →
target	target	target	L	host
			Y
0x1A	Memory	Memory		Memory	Memory	XCSR_SB
	data[31-24]	data[23-16]		data[15-8]	data[7-0]

host →	host →	host →	host →	host →
target	target	target	target	target

Dtarget →

L

Y host

FILL_MEM{_WS} is used with the WRITE_MEM{_WS} command to access large blocks of memory. An initial WRITE_MEM{_WS} is executed to set up the starting address of the block and write the first datum. If an initial WRITE_MEM{_WS} is not executed before the first FILL_MEM{_WS}, an illegal command response is returned. The FILL_MEM{_WS} command stores subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent WRITE_MEM{_WS} commands use this address, perform the memory write, increment it by the current operand size, and store the updated address in the temporary register. If the with-status option is specified, the core status byte contained in XCSR[31–24] (XCSR_SB) is returned after the write data. The XCSR status byte reflects the state after the memory write was performed.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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