Freescale Semiconductor MCF51QE128RM manual CSR2 Field Descriptions

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

		Table 18-8. CSR2 Reference Summary (continued)
	Method	Reference Details
	WRITE_DREG	Writes CSR2[31–0] from the BDM interface. Classified as a non-intrusive BDM command.
	WDEBUG Instruction	Writes CSR2[23–0] during the core’s execution of WDEBUG instruction. This instruction is
		a privileged supervisor-mode instruction.
DRc: 0x02 (CSR2)		Access: Supervisor read-only
		BDM read/write

R

W

Power-on Reset

Other

Reset

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PSTBP	0	0	0	0	0		0	0PSTB	PSTBST		0		D1HRL
						BFHBR		H
							BDFR
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0	0	u	u	u	0	u	0	0	0	0	0	0	0	0	0

15 14 13 12

11 10 9 8

7 6 5 4

3 2 1 0

R

W

Reset

	PSTBWA	0	APCD	0	PSTBRM			PSTBSS
			IV16
		PSTBR
Unaffected and Undefined		0	0	0	0	0	0	0	0

		Figure 18-5. Configuration/Status Register 2 (CSR2)
		Table 18-9. CSR2 Field Descriptions
Field		Description
31	PST buffer stop. Signals if a PST buffer stop condition has been reached.
PSTBP	0	A PST trace buffer stop condition has not been reached
	1	A PST trace buffer stop condition has been reached
30–26	Reserved, must be cleared.
25	BDM force halt on BDM reset. Determines operation of the device after a BDM reset. This bit is cleared after a
BFHBR	power-on reset and is unaffected by any other reset.
	0	The device enters normal operation mode following a BDM reset.
	1	The device enters in halt mode following a BDM reset, as if the BKGD pin was held low after a power-on-reset
	or standard BDM-initiated reset.
24	Background debug force reset. Forces a BDM reset to the device. This bit always reads as 0 after the reset has
BDFR	been initiated.
	0	No reset initiated.
	1	Force a BDM reset.
20	Reserved, must be cleared.
23	PST trace buffer halt. Indicates if the processor is halted due to the PST trace buffer being full when recording in
PSTBH	a continuous mode.
	0	PST trace buffer not full
	1	CPU halted due to PST trace buffer being full in continuous mode

MCF51QE128 MCU Series Reference Manual, Rev. 3

368 Freescale Semiconductor

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