Freescale Semiconductor MCF51QE128RM CPU Halt Sources, Halt Source Halt Timing Description

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

The BDC provides a single-wire debug interface to the target MCU. As shown in the Version 1 ColdFire core block diagram of Figure 18-1, the BDC module interfaces between the single-pin (BKGD) interface and the remaining debug modules, including the ColdFire background debug logic, the real-time debug hardware, and the PST/DDATA trace logic. This interface provides a convenient means for programming the on-chip flash and other non-volatile memories. The BDC is the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as run/halt control, read/write of core registers, breakpoints, and single instruction step.

Features of the background debug controller (BDC) include:

•Single dedicated pin for mode selection and background communications

•Special BDC registers not located in system memory map

•SYNC command to determine target communications rate

•Non-intrusive commands for memory access

•Active background (halt) mode commands for core register access

•GO command to resume execution

•BACKGROUND command to halt core or wake CPU from low-power modes

•Oscillator runs in stop mode, if BDM enabled

Based on these features, BDM is useful for the following reasons:

•In-circuit emulation is not needed, so physical and electrical characteristics of the system are not affected.

•BDM is always available for debugging the system and provides a communication link for upgrading firmware in existing systems.

•Provides high-speed memory downloading, especially useful for flash programming

•Provides absolute control of the processor, and thus the system. This feature allows quick hardware debugging with the same tool set used for firmware development.

18.4.1.1CPU Halt

Although certain BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority. Recall that the default configuration of the Version 1 ColdFire core (CF1Core) defines the occurrence of certain exception types to automatically generate a system reset. Some of these fault types include illegal instructions, privilege errors, address errors, and bus error terminations, with the response under control of the processor’s CPUCR[ARD, IRD] bits.

		Table 18-23. CPU Halt Sources
Halt Source	Halt Timing		Description
		Refers to the occurrence of any fault while exception processing. For example, a bus error is
		signaled during exception stack frame writes or while fetching the first instruction in the
Fault-on-fault	Immediate	exception service routine.
		CPUCR[ARD] = 1	Immediately enters halt.
		CPUCR[ARD] = 0	Reset event is initiated.
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