Freescale Semiconductor MCF51QE128RM Functional Description, Instruction Set Architecture Isac

	ColdFire Core
	Table 7-4. SR Field Descriptions (continued)
Field	Description
10–8	Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
I	equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
7–0	Refer to Section 7.2.4, “Condition Code Register (CCR)”.
CCR

7.3Functional Description

7.3.1Instruction Set Architecture (ISA_C)

The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes based on extensive analysis of embedded application code. The ISA was optimized for code compiled from high-level languages where the dominant operand size was the 32-bit integer declaration. This approach minimized processor complexity and cost, while providing excellent performance for compiled applications.

After the initial ColdFire compilers were created, developers noted there were certain ISA additions that would enhance code density and overall performance. Additionally, as users implemented ColdFire-based designs into a wide range of embedded systems, they found certain frequently-used instruction sequences that could be improved by the creation of additional instructions.

The original ISA definition minimized support for instructions referencing byte- and word-sized operands. Full support for the move byte and move word instructions was provided, but the only other opcodes supporting these data types are clr (clear) and tst (test). A set of instruction enhancements has been implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas:

1.Enhanced support for byte and word-sized operands

2.Enhanced support for position-independent code

3.Miscellaneous instruction additions to address new functionality

Table 7-5summarizes the instructions added to revision ISA_A to form revision ISA_C. For more details see the ColdFire Family Programmer’s Reference Manual.

Table 7-5. Instruction Enhancements over Revision ISA_A

Instruction	Description
BITREV	The contents of the destination data register are bit-reversed; that is, new Dn[31] equals old
	Dn[0], new Dn[30] equals old Dn[1], ..., new Dn[0] equals old Dn[31].
BYTEREV	The contents of the destination data register are byte-reversed; that is, new Dn[31:24] equals
	old Dn[7:0], ..., new Dn[7:0] equals old Dn[31:24].
FF1	The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
	with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
	loaded with the offset count from bit 31 where the first set bit appears.
MOV3Q.L	Moves 3-bit immediate data to the destination location.

	MCF51QE128 MCU Series Reference Manual, Rev. 3
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