Freescale Semiconductor MCF51QE128RM manual Cpucrird =

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

		Table 18-23. CPU Halt Sources (continued)
Halt Source	Halt Timing			Description
Hardware		Halt is made pending in the processor. The processor samples for pending halt and interrupt
	Pending	conditions once per instruction. When a pending condition is asserted, the processor halts
breakpoint trigger
		execution at the next sample point.
			CPUCR[IRD] = 0	A reset is initiated since attempted execution of an
		BDM disabled		illegal instruction
			CPUCR[IRD] = 1	An illegal instruction exception is generated.
		BDM enabled,	Processor immediately halts execution at the next instruction sample
			point. The processor can be restarted by a BDM GO command.
		supervisor mode
			Execution continues at the instruction after HALT.
HALT instruction	Immediate		CSR[UHE] = 0	A reset event is initiated, since a privileged instruction
			CPUCR[IRD] = 0	was attempted in user mode.
			CSR[UHE] = 0	A privilege violation exception is generated.
		BDM enabled,	CPUCR[IRD] = 1
		user mode
				Processor immediately halts execution at the next
			CSR[UHE] = 1	instruction sample point. The processor can be
				restarted by a BDM GO command. Execution
				continues at the instruction after HALT.
		BDM disabled or	Illegal command response and BACKGROUND command is ignored.
		flash secure
				Halt is made pending in the processor. The processor
			Processor is	samples for pending halt and interrupt conditions
				once per instruction. When a pending condition is
			running
				asserted, the processor halts execution at the next
BACKGROUND	Pending			sample point.
command		BDM enabled and
				Processing of the BACKGROUND command is
		flash unsecure
				treated in a special manner. The processor exits the
			Processor is	stopped mode and enters the halted state, at which
				point all BDM commands may be exercised. When
			stopped
				restarted, the processor continues by executing the
				next sequential instruction (the instruction following
				STOP).

MCF51QE128 MCU Series Reference Manual, Rev. 3

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