Freescale Semiconductor MCF51QE128RM CSR Field Descriptions, Bstat FOF TRG Halt Bkpt HRL BKD IPW

Models: MCF51QE128RM

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Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

DRc[4:0]: 0x00 (CSR)

31

30

29

28

27 26 25 24

23 22 21 20

Access: Supervisor write-only BDM read/write

19 18 17 16

R

W Reset

 

BSTAT

 

FOF

TRG

HALT

BKPT

 

 

HRL

 

0

BKD

0

IPW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11 10 9 8

7

6

5

4

3 2 1 0

R

W Reset

0

TRC

0

 

DDC

UHE

 

BTB

0

NPL

IPI

SSM

0

0

FID

DDH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

 

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 18-3. Configuration/Status Register (CSR)

 

 

Table 18-5. CSR Field Descriptions

 

 

 

 

 

Field

 

 

 

Description

 

 

31–28

Breakpoint status. Provides read-only status (from the BDM port only) information concerning hardware

BSTAT

breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or

 

a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.

 

0000

No breakpoints enabled

 

0001

Waiting for level-1 breakpoint

 

0010

Level-1 breakpoint triggered

 

0101

Waiting for level-2 breakpoint

 

0110

Level-2 breakpoint triggered

 

 

27

Fault-on-fault. Indicates a catastrophic halt occurred and forced entry into BDM. FOF is cleared by reset or when

FOF

CSR is read (from the BDM port only).

 

 

26

Hardware breakpoint trigger. Indicates a hardware breakpoint halted the processor core and forced entry into

TRG

BDM. Reset, the debug GO command, or reading CSR (from the BDM port only) clears TRG.

 

 

25

Processor halt. Indicates the processor executed a HALT and forced entry into BDM. Reset, the debug GO

HALT

command, or reading CSR (from the BDM port only) clears HALT.

 

 

 

 

24

Breakpoint assert. Indicates the

 

input was asserted or a BDM BACKGROUND command received, forcing

BKPT

BKPT

the processor into a BDM halt. Reset, the debug GO command, or reading CSR (from the BDM port only) clears

 

BKPT.

 

 

 

 

 

23–20

Hardware revision level. Indicates, from the BDM port only, the level of debug module functionality. An emulator

HRL

can use this information to identify the level of functionality supported.

 

0000

Revision A

 

0001

Revision B

 

0010

Revision C

 

0011

Revision D

 

1001

Revision B+ (The value used for this device)

 

1011

Revision D+

 

 

19

Reserved, must be cleared.

 

 

 

 

 

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual CSR Field Descriptions, Bstat FOF TRG Halt Bkpt HRL BKD IPW