Freescale Semiconductor MCF51QE128RM manual Synchronize PC to PST/DDATA Signals Non-intrusive

			Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
18.4.1.5.17 SYNC_PC
Synchronize PC to PST/DDATA Signals			Non-intrusive
	0x01
	host →	D
	target	L
		Y

Capture the processor’s current PC (program counter) and display it on the PST/DDATA signals. After the debug module receives the command, it sends a signal to the ColdFire core that the current PC must be displayed. The core responds by forcing an instruction fetch to the next PC with the address being captured by the DDATA logic. The DDATA logic captures a 2- or 3-byte instruction address, based on CSR[9]. If CSR[9] is cleared, then a 2-byte address is captured, else a 3-byte address is captured. The specific sequence of PST and DDATA values is defined as:

1.Debug signals a SYNC_PC command is pending.

2.CPU completes the current instruction.

3.CPU forces an instruction fetch to the next PC, generating a PST = 0x5 value indicating a taken branch. DDATA captures the instruction address corresponding to the PC. DDATA generates a PST marker signalling a 2- or 3-byte address as defined by CSR[9] and displays the captured PC address.

This command can be used to provide a PC synchronization point between the core’s execution and the application code in the PST trace buffer. It can also be used to dynamically access the PC for performance monitoring as the execution of this command is considerably less obtrusive to the real-time operation of an application than a BACKGROUND/read-PC/GO command sequence.

18.4.1.5.18 WRITE_CREG

Write CPU control register Active Background

0xC0+CRN

CREG data	CREG data	CREG data	CREG data
[31–24]	[23–16]	[15–8]	[7–0]

host →	host →	host →	host →	host →	D
target	target	target	target	target	L
					Y

If the processor is halted, this command writes the 32-bit operand to the selected control register. This register grouping includes the PC, SR, CPUCR, VBR, and OTHER_A7. Accesses to processor control registers are always 32-bits wide, regardless of implemented register width. The register is addressed through the core register number (CRN). See Table 18-24for the CRN details when CRG is 11.

If the processor is not halted, this command is rejected as an illegal operation and no operation is performed.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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