Freescale Semiconductor MCF51QE128RM manual CPU / Power Mode Selections, Pmc

Chapter 3 Modes of Operation

Table 3-1. CPU / Power Mode Selections

	SOPT1		CSR2	SPMSC1		SPMSC2			Effects on Sub-System
	SIM		BDC	PMC		PMC
Mode of Operation								CPU and
	STOPE		1					Peripheral Clocks
		WAITE	ENBDM	LVDE	LVDSE	LPR	PPDC			Switched
									BDC Clock
										Power
Run mode - processor and peripherals clocked			x	x	x	0	x		On
normally.
	x	x	x	1	1	x	x	On. ICS in any	Note: When not	On
								mode
			1	x	x	x	x		needed, the BDC
									clock can be gated
LPrun mode with low voltage detect disabled -			0	0	x				off at the discretion
								Low freq required.	of the processor.
processor and peripherals clocked at low									The clock is
frequency2.	x	x	0	1	0	1	0	ICS in FBELP	available within a	Loose Reg
Low voltage detects are not active.								mode.	few cycles of
									demand by the
Wait mode - processor clock nominally inactive, but			x	x	x	0	x	Periph clocks on.	processor,
peripherals are clocked.								CPU clock on if	normally when a
	x	1	x	1	1	x	x	ENBDM=1.	negative edge is	On
									detected on
			1	x	x	x	x	On	BKGD. The BDM
									command
LPwait mode - processor clock is inactive,				0	x			CPU clock is off.	associated with
									that negative edge
peripherals are clocked at low frequency and the	x	1	0			1	0	Periph clocks at		Loose Reg
PMC is loosely regulating.								low speed.	may not take
				1	0				affect.
Low voltage detects are not active.								ICS in FBELP.
Stop modes disabled; Illegal opcode reset if STOP			Function
instruction executed and CPUCR[IRD] is cleared,	0	0	of BKGD/	⇒1	⇒1	⇒0	⇒0	⇒On	Function of	⇒On
else illegal instruction exception is generated.			MS at						BKGD/MS at reset
			reset
Stop4 - Either low-power modes have not been			x	x	x	0	0
requested, or low voltage detects are enabled or								Peripheral clocks
ENBDM = 1.			x	1	1	1	0	off. CPU clock on if	BDC clock enabled
	1	0						ENBDM=1.	only if ENBDM=1	On
			x	1	1	0	1		prior to entering
									stop.
			1	x	x	x	x	CPU clock on.
								Periph clocks off.
Stop3 - Low voltage detect in stop is not enabled.				1	0			Low freq required.
Clocks must be at low frequency and are gated. The	1	0	0			1	0	ICS in FBELP
regulator is in loose regulation.								mode. CPU and	Off	Loose Reg
				0	x			peripheral clocks
								are gated off.
Stop2 - Low voltage detects are not active. If BDC is				1	0
enabled, stop4 is invoked rather than stop2.	1	0				0	1	N/A	N/A	Off
				0	x

1ENBDM is located in the upper byte of the XCSR register which is write-accessible only through BDC commands, see Section 18.3.2, “Extended Configuration/Status Register (XCSR)”.

2250 kHz maximum CPU frequency in LPrun; 125 kHz maximum peripheral clock frequency.

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 45

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