Freescale Semiconductor MCF51QE128RM manual Eseqc W, Sec R, Erase W

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

		Table 18-7. XCSR Field Descriptions (continued)
Field		Description
29–27	During reads, indicates the BDM command status.
CSTAT (R)	000 Command done, no errors
ESEQC (W)	001 Command done, data invalid
	01x Command done, illegal
	1xx Command busy, overrun
	If an overrun is detected (CSTAT = 1xx), the following sequence is suggested to clear the source of the error:
	1. Issue a SYNC command to reset the BDC channel.
	2. The host issues a BDM NOP command.
	3. The host checks the channel status using a READ_XCSR_BYTE command.
	4. If XCSR[CSTAT] = 000
		then status is okay; proceed
		else
		Halt the CPU with a BDM BACKGROUND command
		Repeat steps 1,2,3
		If XCSR[CSTAT] ≠ 000, then reset device
	During writes, the ESEQC field is used for the erase sequence control during flash programming. ERASE must
	also be set for this bit to have an effect.
	000 User mass erase
	Else Reserved
	Note: See Figure 4-15for a detailed description of the algorithm for clearing of security.
26	Select source for serial BDC communication clock.
CLKSW	0	Alternate, asynchronous BDC clock, typically 10 MHz
	1	Synchronous bus clock (CPU clock divided by 2)
	The initial state of the XCSR[CLKSW] bit is loaded by the hardware in response to certain reset events and the
	state of the BKGD pin as described in Figure 18-2.
25	The read value of this bit typically defines the status of the flash security field:
SEC (R)	0	Flash security is disabled
ERASE (W)	1	Flash security is enabled
	In addition, the SEC bit is context-sensitive during reads. Once a mass-erase sequence has been initiated by
	BDM, it acts as a flash busy flag. When the erase operation is complete and the bit is cleared, it returns to reflect
	the status of the chip security.
	0	Flash is not busy performing a BDM mass-erase sequence
	1	Flash is busy performing a BDM mass-erase sequence
	During writes, this bit qualifies XCSR[ESEQC] for the write modes shown in the ESEQC field description.
	0	Do not perform a mass-erase of the flash.
	1	Perform a mass-erase of the flash, using the sequence specified in the XCSR[ESEQC] field.
24	Enable BDM.
ENBDM	0	BDM mode is disabled
	1	Active background mode is enabled (assuming the flash is not secure)
23–3	Reserved for future use by the debug module, must be cleared.

MCF51QE128 MCU Series Reference Manual, Rev. 3

366 Freescale Semiconductor

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