Freescale Semiconductor MCF51QE128RM manual 21signal timing is not drawn to scale

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

any of the stop modes. If the host aborts a command by sending the sync pulse, it should then read XCSR[CSTAT] after the sync response is issued by the target, checking for CSTAT cleared, before attempting to send any new command that requires CPU execution. This prevents the new command from being discarded at the debug/CPU interface, due to the pending command being executed by the CPU. Any new command should be issued only after XCSR[CSTAT] is cleared.

There are multiple reasons that could cause a command to take too long to execute, measured in terms of the serial communication rate. Either the BDC clock frequency is much faster than the CPU clock frequency, or the CPU is accessing a slow memory, which would cause pipeline stall cycles to occur. All commands referencing the CPU registers or memory require access to the processor’s local bus to complete. If the processor is executing a tight loop that is contained within a single aligned longword, the processor may never successfully grant the internal bus to the debug command. For example:

label1:	align	4
	nop	label1
or	bra.b
label2:	align	4
	bra.w	label2

These two examples of tight loops both exhibit the BDM lockout behavior. If the loop spans across two longwords, there are no issues, so the recommended construct is:

align	4
label3: bra.l	label3

The hardware handshake protocol is appropriate for these situations, but the host could also decide to use the software handshake protocol instead. In this case, if XCSR[CSTAT] is 001, there is a BDC command pending at the debug/CPU interface. The host controller should monitor XCSR[CSTAT] and wait until it is 000 in order to be able to issue a new command that requires CPU execution. However, if the XCSR[CSTAT] is 1xx, the host should assume the last command failed to execute. To recover from this condition, the following sequence is suggested:

1.Issue a SYNC command to reset the BDC communication channel.

2.The host issues a BDM NOP command.

3.The host reads the channel status using a READ_XCSR_BYTE command.

4.If XCSR[CSTAT] is 000

then the status is okay; proceed else

Halt the CPU using a BDM BACKGROUND command Repeat steps 1,2,3

If XCSR[CSTAT] is 000, then proceed, else reset the device

Figure 18-21shows a SYNC command aborting a READ_BYTE. Note that after the command is aborted, a new command could be issued by the host.

NOTE

Figure 18-21signal timing is not drawn to scale.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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