Freescale Semiconductor MCF51QE128RM manual System Options Register 2 SOPT2

7

				Table 5-4. SOPT1 Register Field Descriptions
Field				Description
7	COP Watchdog Enable. This write-once bit selects whether the COP watchdog is enabled.
COPE	0 COP watchdog timer disabled.
	1 COP watchdog timer enabled (force reset on timeout).
6	COP Watchdog Timeout. This write-once bit selects the timeout period of the COP. COPT along with
COPT	SOPT2[COPCLKS] defines the COP timeout period.
	0 Short timeout period selected.
	1 Long timeout period selected.
5	Stop Mode Enable. This write-once bit is used to enable stop mode. If stop and wait modes are disabled and a
STOPE	user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending on
	CPUCR[IRD].
4	Wait Mode Enable. This write-anytime bit is used to enable wait mode. If stop and wait modes are disabled and
WAITE	a user program attempts to execute a STOP instruction, an illegal opcode reset may be generated depending on
	CPUCR[IRD]. If this bit is set, the value of STOPE is ignored when the STOP instruction is executed.
	Note: The user must execute a NOP instruction following any change to WAITE to allow the updated register bit
		time to propagate to the processor.
3	Reserved, should be cleared.
2		Pin Enable. When set, this write-once bit enables the PTC4/RGPIO12/TPM3CH4/RSTO					pin to function as
	RSTO
RSTOPE	RSTO	When clear, the pin functions as one of its alternative functions. This pin defaults to its I/O port function
	following an MCU POR. When RSTOPE is set, an internal pullup device is enabled on				RSTO.		The pin remains
	in this mode until the next power-on-reset.
1	Background Debug Mode Pin Enable. When set, this write-once bit enables the PTA4/ACMP1O/BKGD/MS pin
BKGDPE	to function as BKGD/MS. When clear, the pin functions as one of its output-only alternative functions. This pin
	defaults to the BKGD/MS function following any MCU reset.
0						pin to function as
	RESET			Pin Enable. This write-once bit when set enables the PTA5/IRQ/TPM1CLK/RESET
RSTPE	RESET.		When clear, the pin functions as one of its input-only alternative functions. This pin defaults to its I/O port
	function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on						RESET.

5.7.4System Options Register 2 (SOPT2)

This high page register contains bits to configure MCU specific features on the MCF51QE128/64/32 devices.

6 5 4

3 2 1 0

R	COPCLKS1	0	0	0	SPI1PS	ACIC2	IICPS	ACIC1
W
Reset:	0	0	0	0	0	0	0	0

1This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-4. System Options Register 2 (SOPT2)

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 101

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