Freescale Semiconductor MCF51QE128RM manual Extended Configuration/Status Register Xcsr

Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)

		Table 18-5. CSR Field Descriptions (continued)
Field		Description
5	Ignore pending interrupts when in single-step mode.
IPI	0	Core services any pending interrupt requests signalled while in single-step mode.
	1	Core ignores any pending interrupt requests signalled while in single-step mode.
4	Single-step mode enable.
SSM	0	Normal mode.
	1	Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command
		can be executed. On receipt of the GO command, the processor executes the next instruction and halts again.
		This process continues until SSM is cleared.
3–2	Reserved, must be cleared.
1	Force ipg_debug. The core generates this output to the device, signaling it is in debug mode.
FID	0	Do not force the assertion of ipg_debug
	1	Force the assertion of ipg_debug
0	Disable ipg_debug due to a halt condition. The core generates an output to the other modules in the device,
DDH	signaling it is in debug mode. By default, this output signal is asserted whenever the core halts.
	0	Assert ipg_debug if the core is halted
	1	Negate ipg_debug due to the core being halted

18.3.2Extended Configuration/Status Register (XCSR)

The 32-bit XCSR is partitioned into two sections: the upper byte contains status and command bits always accessible to the BDM interface, even if debug mode is disabled. This status byte is also known as XCSR_SB. The lower 24 bits contain fields related to the generation of automatic SYNC_PC commands, which can be used to periodically capture and display the current program counter (PC) in the PST trace buffer (if properly configured).

There are multiple ways to reference the XCSR. They are summarized in Table 18-6.

Table 18-6. XCSR Reference Summary

Method	Reference Details
READ_XCSR_BYTE	Reads XCSR[31–24] from the BDM interface. Available in all modes.
WRITE_XCSR_BYTE	Writes XCSR[31–24] from the BDM interface. Available in all modes.
READ_DREG	Reads XCSR[31–0] from the BDM interface. Classified as a non-intrusive BDM command.
WRITE_DREG	Writes XCSR[31–0] from the BDM interface. Classified as a non-intrusive BDM command.
WDEBUG instruction	Writes XCSR[23–0] during the core’s execution of WDEBUG instruction. This instruction
	is a privileged supervisor-mode instruction.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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