Freescale Semiconductor MCF51QE128RM manual Section Number Title

Section Number			Title	Page
3.7	Wait Modes			50
	3.7.1	Wait Mode	.........................................................................................................................	50
	3.7.2 Low-Power Wait Mode (LPwait)			50
		3.7.2.1	BDM in Low-Power Wait Mode	50
3.8	Stop Modes			50
	3.8.1	Stop2 Mode		51
		3.8.1.1	Low-Range Oscillator Considerations for Stop2	52
	3.8.2	Stop3 Mode		52
	3.8.3 Stop4: Low Voltage Detect or BDM Enabled in Stop Mode			52
3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes				53
			Chapter 4
			Memory
4.1	MCF51QE128/64/32 Memory Map			57
4.2 Register Addresses and Bit Assignments				58
	4.2.1 Flash Module Reserved Memory Locations			67
	4.2.2 ColdFire Rapid GPIO Memory Map			69
	4.2.3 ColdFire Interrupt Controller Memory Map			69
4.3	RAM			70
4.4	Flash			70
	4.4.1	Features		71
	4.4.2	Register Descriptions		72
		4.4.2.1 Flash Clock Divider Register (FCDIV)		72
		4.4.2.2 Flash Options Register (FOPT and NVOPT)		72
		4.4.2.3 Flash Configuration Register (FCNFG)		73
		4.4.2.4 Flash Protection Register (FPROT and NVPROT)		74
		4.4.2.5 Flash Status Register (FSTAT)		76
		4.4.2.6 Flash Command Register (FCMD)		77
4.5	Function Description			77
	4.5.1	Flash Command Operations		77
		4.5.1.1 Writing the FCDIV Register		78
		4.5.1.2	Command Write Sequence	79
	4.5.2	Flash Commands		80
		4.5.2.1	Erase Verify Command	80
		4.5.2.2	Program Command	81
		4.5.2.3	Burst Program Command	83
		4.5.2.4	Sector Erase Command	84
		4.5.2.5	Mass Erase Command	86
	4.5.3	Illegal Flash Operations		87
		4.5.3.1	Flash Access Violations	87
		4.5.3.2	Flash Protection Violations	88
	4.5.4	Operating Modes		88
			MCF51QE128 MCU Series Reference Manual, Rev. 3
8				Freescale Semiconductor
			Get the latest version from freescale.com