Freescale Semiconductor MCF51QE128RM manual Status and Control Register 2 ADCSC2, Adact

Analog-to-Digital Converter (S08ADC12V1)

11.3.2Status and Control Register 2 (ADCSC2)

The ADCSC2 register controls the compare function, conversion trigger, and conversion active of the ADC module.

R

W Reset:

7	6	5	4	3	2	1	0
ADACT	ADTRG	ACFE	ACFGT	0	0	R1	R1
0	0	0	0	0	0	0	0

Figure 11-4. Status and Control Register 2 (ADCSC2)

1Bits 1 and 0 are reserved bits that must always be written to 0.

		Table 11-5. ADCSC2 Register Field Descriptions
Field		Description
7	Conversion Active. Indicates that a conversion is in progress. ADACT is set when a conversion is initiated and
ADACT	cleared when a conversion is completed or aborted.
	0	Conversion not in progress
	1	Conversion in progress
6	Conversion Trigger Select. Selects the type of trigger used for initiating a conversion. Two types of trigger are
ADTRG	selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated
	following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion
	of the ADHWT input.
	0	Software trigger selected
	1	Hardware trigger selected
5	Compare Function Enable. Enables the compare function.
ACFE	0	Compare function disabled
	1	Compare function enabled
4	Compare Function Greater Than Enable. Configures the compare function to trigger when the result of the
ACFGT	conversion of the input being monitored is greater than or equal to the compare value. The compare function
	defaults to triggering when the result of the compare of the input being monitored is less than the compare value.
	0	Compare triggers when input is less than compare level
	1	Compare triggers when input is greater than or equal to compare level

11.3.3Data Result High Register (ADCRH)

In 12-bit operation, ADCRH contains the upper four bits of the result of a 12-bit conversion. In 10-bit mode, ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 10-bit mode, ADR[11:10] are cleared. When configured for 8-bit mode, ADR11 – ADR8 are equal to zero.

In 12-bit and 10-bit mode, ADCRH is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, the intermediate conversion result is lost. In 8-bit mode, there is no interlocking with ADCRL.

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 223

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