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Freescale Semiconductor MCF51QE128RM manual IIC Status Register Iics, Iics Field Descriptions, Tcf

Models: MCF51QE128RM

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13.3.4IIC Status Register (IICS)

R

W

Reset

7	6	5		4	3	2	1	0
TCF	IAAS	BUSY		ARBL	0	SRW	IICIF	RXAK



1	0	0		0	0	0	0	0
	= Unimplemented or Reserved
	= Unimplemented or Reserved

		Figure 13-6. IIC Status Register (IICS)
		Table 13-7. IICS Field Descriptions

Field		Description

7	Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or
TCF	immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the
	IICD register in receive mode or writing to the IICD in transmit mode.
	0	Transfer in progress
	1	Transfer complete

6	Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address or
IAAS	when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit.
	0	Not addressed
	1	Addressed as a slave

5	Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set
BUSY	when a start signal is detected and cleared when a stop signal is detected.
	0	Bus is idle
	1	Bus is busy

4	Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared
ARBL	by software by writing a 1 to it.
	0	Standard bus operation
	1	Loss of arbitration

2	Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the
SRW	calling address sent to the master.
	0	Slave receive, master writing to slave
	1	Slave transmit, master reading from slave

1	IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing
IICIF	a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
		• One byte transfer completes
		• Match of slave address to calling address
		• Arbitration lost
	0	No interrupt pending
	1	Interrupt pending

0	Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after the
RXAK	completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
	signal is detected.
	0	Acknowledge received
	1	No acknowledge received

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor

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Freescale Semiconductor MCF51QE128RM manual IIC Status Register Iics, Iics Field Descriptions, Tcf

Contents

MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Chapter Resets, Interrupts, and General System Control Freescale SemiconductorTitle Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Section Number Title Chapter Inter-Integrated Circuit S08IICV2Real-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History MCF51QE128 Series Features by MCU and Package Feature MCF51QE128Chapter Device Overview Devices in the MCF51QE128/64/32 SeriesMCU Block Diagram XoscMCF51QE128/64/32 Block Diagram V1 ColdFire Core System ClocksInternal Clock Source ICS Module Module VersionsSimplified ICS Block Diagram System Clock DistributionIcsirclk FLL Bypassed Internal Low-Power Fbilp ICS Modes of OperationFLL Engaged Internal FEI FLL Engaged External FEEFLL Bypassed External Low-Power Fbelp Stop StopGet the latest version from freescale.com Get the latest version from freescale.com Chapter Pins and Connections Device Pin AssignmentPins in bold are added from the next smaller package Pin LqfpRecommended System Connections Basic System Connections Reset and Rsto PowerOscillator Background / Mode Select BKGD/MS ADC Reference Pins VREFH, Vrefl General-Purpose I/O and Peripheral PortsPin Assignment by Package and Pin Sharing Priority PinPriority Number Port Pin AltNumber Port Pin AltGet the latest version from freescale.com Chapter Modes of Operation FeaturesIntroduction MCF51QE128/64/32 Power Modes Conceptual Drawing OverviewCPU / Power Mode Selections PMCMode Regulator State Stop3Full On Run Stop2 LPrunTriggers for Transitions Shown in Figure Transition # From TriggerDebug Mode Secure ModeRun Mode Low-Power Run Mode LPrunBDM in Low-Power Run Mode Run ModesWait Mode Low-Power Wait Mode LPwaitBDM in Low-Power Wait Mode Wait ModesStop2 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop Mode Stop3 ModeLow-Range Oscillator Considerations for Stop2 On-Chip Peripheral Modules in Stop and Low-Power Modes Low-Power Mode BehaviorAbbreviations used in Table CF1COREBDC COPICS IRQGet the latest version from freescale.com Get the latest version from freescale.com Chapter Memory MCF51QE128/64/32 Memory MapKbytes RAMCPU Access Type Allowed by Region Register Addresses and Bit AssignmentsRead Write Base Address Region Byte Long ByteColdFire Memory Organization Direct-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 2 Register Address NameDirect-Page Register Summary Sheet 3 Direct-Page Register Summary Sheet 4 High-Page Register Summary Sheet 1High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 Flash Module Reserved Memory Locations High-Page Register Summary Sheet 5Reserved Flash Memory Addresses 0x0 0x1 0x2 0x30x0 0x1 0x2 0x3 0x00000408 0x0000040CReserved Flash Memory Addresses Register NvprotColdFire Rapid Gpio Memory Map ColdFire Interrupt Controller Memory MapV1 ColdFire Rapid Gpio Memory Map V1 ColdFire Interrupt Controller Memory MapRAM FlashIntcsfrc IntccfrcLov-Voltage Programming Sequence Example FeaturesAddresses Desired Value Values Programmed Register Descriptions Flash Clock Divider Register FcdivFlash Options Register Fopt and Nvopt Fcdiv Field DescriptionsFlash Configuration Register Fcnfg 10. Fopt Field DescriptionsFlash Protection Register Fprot and Nvprot 11. Fcnfg Field Descriptions12. Fprot Field Descriptions 13. Flash Protection Address Range0x00-0x3F 0x400x41 0x00000-0x1EFFF 0x42Command buffers are full Flash Status Register FstatFcbef Fccf Fpviol Faccerr Fblank W1cFlash Command Operations Flash Command Register FcmdFunction Description 15. Fcmd Field DescriptionsWriting the Fcdiv Register 200 195 ⎟ 200 = 3%Command Write Sequence Commands ImpossibleStart ALL Program and EraseFlash Commands Erase Verify Command16. Flash Command Description Fcmd NVMProgram Command 11. Example Program Command Flow Burst Program Command Sector Erase Command Command Buffer EmptySequential Programming13. Example Sector Erase Command Flow Mass Erase Command 14. Example Mass Erase Command FlowFlash Access Violations Illegal Flash OperationsWait Mode Background Debug ModeOperating Modes Flash Protection ViolationsUnsecuring the MCU using Backdoor Key Access SecurityResets Flash Reset SequenceReset While Flash Command Active Program and Erase TimesSecurity Sync Set PRDIV8 and clock divider fields in CSR3Stop Device is unsecureChapter Resets, Interrupts, and General System Control Microcontroller ResetCOP Configuration Options Computer Operating Properly COP WatchdogControl Bits Clock Source COP Overflow Count Copclks CoptIllegal Operation Reset Illegal Address ResetPin Configuration Options Interrupts and ExceptionsPower-On Reset Operation Low-Voltage Detect LVD SystemEdge and Level Sensitivity External Interrupt InitializationLVD Reset Operation Peripheral Clock GatingLVD Interrupt Operation Low-Voltage Warning LVW Interrupt OperationInterrupt Pin Request Status and Control Register Irqsc Irqsc Register Field DescriptionsIrqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack IrqpddSystem Reset Status Register SRS PORSystem Options Register 1 SOPT1 POR LVRSystem Options Register 2 SOPT2 SOPT1 Register Field DescriptionsSystem Device Identification Register SDIDH, Sdidl SOPT2 Register Field DescriptionsSPI1PS SPSCLK1 MOSI1 MISO1 SS1 IIC1PS SDA1 SCL1Sdidl Register Field Descriptions Sdidh Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack SPMSC1 Register Field Descriptions LPR Lprs Lpwui Ppde Ppdc PpdackSPMSC2 Register Field Descriptions 11. LVD and LVW Trip Point Typical Values1 Lvwf Lvdv Lvwv LvwieLvwf LvdvlvwvSystem Clock Gating Control 1 Register SCGC1 System Clock Gating Control 2 Register SCGC212. SCGC1 Register Field Descriptions TPM3RTC SPI2 SPI1 13. SCGC2 Register Field DescriptionsFLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Port Data and Data Direction Chapter Parallel Input/Output ControlFreescale Semiconductor 113 Port Internal Pull-up Enable Port Slew Rate EnablePull-up, Slew Rate, and Drive Strength Data Direction Control Port Data Register Port ReadPort Drive Strength Select Port Data Set, Clear and Toggle Data RegistersFreescale Semiconductor 115 V1 ColdFire Rapid Gpio Functionality Keyboard InterruptsPort Data Set Registers Port Data Clear RegistersEdge Only Sensitivity Edge and Level SensitivityPull-up/Pull-down Resistors Freescale Semiconductor 117Pin Behavior in Stop Modes Parallel I/O, Keyboard Interrupt, and Pin Control RegistersKeyboard Interrupt Initialization Port a RegistersPort a Pull Enable Register Ptape Port a Data Register PtadPort a Data Direction Register Ptadd PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0Port a Slew Rate Enable Register Ptase Port a Drive Strength Selection Register PtadsPTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0Port B Registers Port B Data Register PtbdPort B Data Direction Register Ptbdd Ptads Register Field DescriptionsPort B Pull Enable Register Ptbpe Port B Slew Rate Enable Register PtbsePtbdd Register Field Descriptions Ptbpe Register Field DescriptionsPort C Registers Port B Drive Strength Selection Register PtbdsPort C Data Register Ptcd 10. Ptbds Register Field DescriptionsPort C Data Direction Register Ptcdd Port C Data Set Register PtcsetPort C Data Clear Register Ptcclr 12. Ptcdd Register Field DescriptionsPort C Pull Enable Register Ptcpe Port C Toggle Register Ptctog14. Ptcclr Register Field Descriptions 16. Ptcpe Register Field DescriptionsPort C Slew Rate Enable Register Ptcse Port D RegistersPort C Drive Strength Selection Register Ptcds Port D Data Register PtddPort D Pull Enable Register Ptdpe Port D Data Direction Register Ptddd19. Ptdd Register Field Descriptions 20. Ptddd Register Field DescriptionsPort D Slew Rate Enable Register Ptdse Port E RegistersPort D Drive Strength Selection Register Ptdds Port E Data Register PtedPort E Data Direction Register Ptedd Port E Data Set Register Pteset24. Pted Register Field Descriptions 25. Ptedd Register Field DescriptionsPort E Pull Enable Register Ptepe Port E Data Clear Register PteclrPort E Toggle Register Ptetog PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0Port E Slew Rate Enable Register Ptese Port E Drive Strength Selection Register Pteds29. Ptepe Register Field Descriptions 30. Ptese Register Field DescriptionsPort F Pull Enable Register Ptfpe Port F RegistersPort F Data Register Ptfd Port F Data Direction Register PtfddPort F Slew Rate Enable Register Ptfse Port F Drive Strength Selection Register Ptfds34. Ptfpe Register Field Descriptions 35. Ptfse Register Field DescriptionsPort G Registers Port G Data Register PtgdPort G Data Direction Register Ptgdd 36. Ptfds Register Field DescriptionsPort G Pull Enable Register Ptgpe Port G Slew Rate Enable Register PtgsePort G Drive Strength Selection Register Ptgds 39. Ptgpe Register Field DescriptionsPort H Registers Port H Data Register PthdPort H Data Direction Register Pthdd 41. Ptgds Register Field DescriptionsPort H Pull Enable Register Pthpe Port H Slew Rate Enable Register PthsePort H Drive Strength Selection Register Pthds 44. Pthpe Register Field DescriptionsPort J Data Register Ptjd Port J RegistersPort J Data Direction Register Ptjdd Port J Pull Enable Register Ptjpe Port J Slew Rate Enable Register PtjsePort J Drive Strength Selection Register Ptjds 49. Ptjpe Register Field DescriptionsKeyboard Interrupt 1 KBI1 Registers 10.1 KBI1 Interrupt Status and Control Register KBI1SC51. Ptjds Register Field Descriptions 52. KBI1 Pin Mapping10.2 KBI1 Interrupt Pin Select Register KBI1PE Keyboard Interrupt 1 KBI2 Registers10.3 KBI1 Interrupt Edge Select Register KBI1ES 11.1 KBI2 Interrupt Status and Control Register KBI2SC 11.2 KBI2 Interrupt Pin Select Register KBI2PE57. KBI2SC Register Field Descriptions 58. KBI2PE Register Field Descriptions59. KBI2ES Register Field Descriptions 11.3 KBI2 Interrupt Edge Select Register KBI2ESFreescale Semiconductor 143 144 Freescale Semiconductor Chapter ColdFire Core OverviewMemory Map/Register Description Supervisor/User Access Registers Supervisor Access Only RegistersData Registers D0-D7 ColdFire Core Programming ModelSupervisor/User Stack Pointers A7 and OTHERA7 Address Registers A0-A6Data Condition Code Register CCR Freescale Semiconductor 149Vector Base Register VBR Program Counter PCCCR Field Descriptions CPU Configuration Register Cpucr SR Field Descriptions Status Register SRBWD Functional Description Instruction Set Architecture IsacInstruction Enhancements over Revision Isaa Instruction DescriptionException Processing Overview Vector Stacked Exception Vector AssignmentsAssignment Numbers Offset Hex Counter Exception Stack Frame Definition AssignmentNumbers Offset Hex Counter SSP →Fault Status Encodings 2.2 S08 and ColdFire Exception Processing ComparisonFormat Field Encodings FS30 DefinitionAttribute S08 V1 ColdFire Exception Processing ComparisonRTI RTE Access Error Exception Address Error ExceptionProcessor Exceptions Freescale Semiconductor 159Illegal Instruction Exception 10. ColdFire Opword Line DefinitionLine OpMode Effective Address OpwordLine Instruction ClassTrace Exception Privilege ViolationFreescale Semiconductor 161 RTE and Format Error Exception Unimplemented Line-A OpcodeUnimplemented Line-F Opcode Debug InterruptFault-on-Fault Halt Trap Instruction ExceptionUnsupported Instruction Exception Interrupt ExceptionReset Exception Access User read-only BDM read-onlyBDM Load 0x60 D0 Store 0x40 D0 VER REV11. D0 Hardware Configuration Info Field Description Flashsz 12. D1 Hardware Configuration Information Field DescriptionSramsz Instruction Execution Timing Timing Assumptions13. Misaligned Operand References Address10 Size Bus Additional Operations CR/WMove Instruction Execution Times 14. Move Byte and Word Execution Times15. Move Long Execution Times Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl16. One Operand Instruction Execution Times Standard One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Standard Two Operand Instruction Execution Times 17. Two Operand Instruction Execution Times18. Miscellaneous Instruction Execution Times Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx 19. General Branch Instruction Execution Times Branch Instruction Execution Times20. Bcc Instruction Execution Times Attribute Chapter Interrupt Controller CF1INTCHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x144 0x148 Next ACMPx 0x14C0x150 Next SCI2rx 0x154 SCI2tx 0x158 0x180 NextTo V1 ColdFire core Interrupt Source NumberFreescale Semiconductor 177 Memory Map and Register Definition External Signal DescriptionModes of Operation Intc Force Interrupt Register Intcfrc Memory MapCF1INTC Memory Map Intcfrc Field Descriptions INTCPL6P7,6 Field Descriptions Intc Wake-up Control Register IntcwcrFreescale Semiconductor 181 Intcwcr Field Descriptions Intc Set Interrupt Force Register IntcsfrcENB Intc Clear Interrupt Force Register Intccfrc Intcsfrc Field DescriptionsIntccfrc Field Descriptions Offset CF1INTCBASE + 0x1F IntccfrcIntc Software and Level-nIACK Registers n = 1,2,3,...,7 Vecn SwiackInterrupt Request Level and Priority Assignments INTCSWIACK, INTCLVLnIACK Field Descriptions10. Legend for Table Priority within Level MidpointTPM1ch0 TPM1ch1 TPM1ch2 TPM1ovfl 12. V1 ColdFire Interrupt AssignmentsTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Application Information Initialization InformationEmulation of the HCS08’s 1-Level IRQ Handling More on Software IACKs Using INTCPL6P7,6 RegistersFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Chapter Rapid Gpio Rgpio Freescale Semiconductor 193V1 ColdFire Core Freescale Semiconductor 195 IFP CoreOEP Dsoc RAM RgpioRgpio ModulePin Muxing + Pad Logic On-platform Bus RGPIODATA150Rgpio Module External I/O Signals Detailed Signal DescriptionsRgpio Detailed Signal Descriptions Rgpio Write Memory Map Memory Map/Register DefinitionRgpio Read Memory Map Rgpio Data Direction Rgpiodir Rgpio Data RgpiodataRgpiodir Field Descriptions DIRRgpio Pin Enable Rgpioenb Rgpio Clear Data RgpioclrRgpio Set Data Rgpioset Rgpio Toggle Data RgpiotogRgpioclr Field Descriptions Rgpioset Field DescriptionsApplication 1 Simple Square-Wave Generation 10. Rgpiotog Field DescriptionsTOG Field Description 15-0 Rgpio Toggle Data11. Square-Wave Output Performance 12. Emulated SPI Performance using Gpio Outputs SPI Speed @ Relative CPU f = 50 MHz29x Freescale Semiconductor 205206 Freescale Semiconductor Acmp Configuration Information ACMP/TPM Configuration InformationChapter Analog Comparator 3V ACMPVLPV1 Acmp Clock GatingInterrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Block Diagram Wait Mode OperationStop3 Mode Operation Stop2 Mode OperationRegister Definition Status and Control Register ACMPxSCAcbgs Acpe Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACFInterrupts ACMPxSC Field DescriptionsAcme Acmod214 Freescale Semiconductor ADC Clock Gating Chapter Analog-to-Digital Converter S08ADC12V1Freescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 Module Configurations Channel AssignmentsAlternate Clock ADC Channel AssignmentTemperature Sensor Hardware Trigger2provides a block diagram of the ADC module Freescale Semiconductor 219Name Function Signal PropertiesAD27-AD0 Analog Power Vddad Analog Ground VssadVoltage Reference High Vrefh Voltage Reference Low VreflInput Channel Select CocoInput Select Status and Control Register 2 ADCSC2 Data Result High Register AdcrhADCSC2 Register Field Descriptions AdactData Result Low Register Adcrl Compare Value High Register AdccvhADR10 ADR9 ADR8 ADCV11 ADCV10 ADCV9 ADCV8Configuration Register Adccfg Compare Value Low Register AdccvlAdccfg Register Field Descriptions AdlpcPin Control 1 Register APCTL1 Clock Divide SelectConversion Modes Input Clock Select10. APCTL1 Register Field Descriptions Pin Control 2 Register APCTL2ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 Pin Control 3 Register APCTL3 11. APCTL2 Register Field DescriptionsADPC15 ADPC2312. APCTL3 Register Field Descriptions ADPC21ADPC20 ADPC16Clock Select and Divide Control Input Select and Pin ControlHardware Trigger Conversion ControlInitiating Conversions Completing ConversionsAborting Conversions Freescale Semiconductor 231Power Control Sample Time and Total Conversion Time13. Total Conversion Time vs. Control Conditions Adiclk AdlsmpMCU Wait Mode Operation Automatic Compare FunctionMCU Stop3 Mode Operation MCU Stop2 Mode OperationStop3 Mode With Adack Disabled Stop3 Mode With Adack EnabledADC Module Initialization Example Initialization SequencePseudo-Code Example Freescale Semiconductor 235External Pins and Routing Reset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check NoCOCO=1? Yes Read Adcrh Then Adcrl To Clear Coco Bit ContinueAnalog Supply Pins Analog Reference PinsAnalog Input Pins Freescale Semiconductor 237Sources of Error Sampling ErrorPin Leakage Error Noise-Induced ErrorsCode Width and Quantization Error Linearity ErrorsLsb = Freescale Semiconductor 239Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor Stop2 Mode Considerations Chapter Internal Clock Source S08ICSV3External Oscillator Freescale Semiconductor 243Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor HGO, RANGE, EREFS, ERCLKEN, Erefsten Freescale Semiconductor 2472is the ICS block diagram FLL Bypassed Internal Low Power Fbilp FLL Bypassed External Low Power FbelpICS Register Summary Rdiv IrefsICS Control Register 1 ICSC1 ICSC1 Field DescriptionsClks Rdiv Irefs Irclken Irefsten Reference Divide FactorICS Control Register 2 ICSC2 ICS Trim Register IcstrmICSC2 Field Descriptions Bdiv Range HGO Erefs Erclken ErefstenICS Status and Control Icssc Icstrm Field DescriptionsIcssc Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRSReference range FLL factor DCO range 512 16 20 MHz608 19.92 MHz 1024 32 40 MHzOperational Modes FLL Engaged Internal FEIIREFS=1 CLKS=00 IREFS=0 IREFS=0 CLKS=10FLL Bypassed Internal Low Power Fbilp FLL Engaged External FEEFLL Bypassed Internal FBI FLL Bypassed External FBEMode Switching FLL Bypassed External Low Power FbelpBus Frequency Divider StopLow Power Bit Usage DCO Maximum Frequency with 32.768 kHz OscillatorInternal Reference Clock External Reference ClockFixed Frequency Clock Local ClockModule Configuration Chapter Inter-Integrated Circuit S08IICV2IIC1 Position Options SOPT2IIC1PSMCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SDA Serial Data Line SCL Serial Clock LineFreescale Semiconductor 263 IIC Address Register Iica IIC Frequency Divider Register IicfIica Field Descriptions = Unimplemented or ReservedIicf Field Descriptions Hold Time Values for 8 MHz Bus SpeedHold Times μs Mult ICR SDAIIC Divider and Hold Values ICR SCLIIC Control Register IICC1 IICC1 Field DescriptionsIics Field Descriptions IIC Status Register IicsTCF IIC Data I/O Register Iicd IIC Control Register 2 IICC2Iicd Field Descriptions Freescale Semiconductor 269IICC2 Field Descriptions IIC ProtocolGcaen Slave Address Transmission Start SignalFreescale Semiconductor 271 Stop Signal Repeated Start SignalArbitration Procedure Data TransferClock Synchronization HandshakingClock Stretching Freescale Semiconductor 273Master-Transmitter Addresses a Slave-Receiver 13.4.2 10-bit AddressMaster-Receiver Addresses a Slave-Transmitter Resets General Call AddressByte Transfer Interrupt Address Detect Interrupt276 Freescale Semiconductor Initialization/Application Information Module Initialization SlaveModule Initialization Master Module Use12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor Chapter Real-Time Counter S08RTCV1 ADC Hardware TriggerRTC Clock Sources RTC Modes of OperationInterrupt Vector MCF51QE128 Block Diagram Highlighting RTC Block and Pins Freescale Semiconductor 283Active Background Mode RTC Register Summary LPOErclk IrclkRTC Status and Control Register Rtcsc Rtcsc Field DescriptionsRTC Prescaler Divide-by values RtifRTC Counter Register Rtccnt RTC Modulo Register RtcmodRtccnt Field Descriptions Rtcmod Field DescriptionsRTC Operation Example Prescaler PeriodRtcps KHz Internal Clock MHz External Clock Rtclks =Internal 1-kHz Clock Source RTC Clock Rtcps = Rtccnt Rtif0x52 0x53 0x54 0x55 0x00 0x01 Freescale Semiconductor 289290 Freescale Semiconductor SCI Clock Gating Chapter Serial Communications Interface S08SCIV4Freescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI SCI Receiver Block Diagram Freescale Semiconductor 297SCIxBDH Field Descriptions SCI Baud Rate Registers SCIxBDH, SCIxBDLLbkdie SCI Control Register 1 SCIxC1 SCIxBDL Field DescriptionsLoops Sciswai Rsrc Wake ILT LoopsSCIxC2 Field Descriptions SCI Control Register 2 SCIxC2TIE SCI Status Register 1 SCIxS1 Tdre Rdrf IdleFraming error No parity errorParity error SCIxDSCI Status Register 2 SCIxS2 SCIxS2 Field DescriptionsLbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF RXINV1SCI Control Register 3 SCIxC3 SCIxC3 Field DescriptionsTxdir TXINV1Baud Rate Generation SCI Data Register SCIxDFreescale Semiconductor 305 Transmitter Functional Description Send Break and Queued IdleReceiver Functional Description Data Sampling TechniqueBreak Character Length BRK13Receiver Wakeup Operation Idle-Line WakeupInterrupts and Status Flags Freescale Semiconductor 309Stop Mode Operation Loop ModeAdditional SCI Functions 15.3.5.1 8- and 9-Bit Data ModesSingle-Wire Operation Freescale Semiconductor 311312 Freescale Semiconductor SPI Clock Gating Chapter Serial Peripheral Interface S08SPIV3Freescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor SPI System Block Diagram Block DiagramsFreescale Semiconductor 317 SPI Module Block Diagram SPI Baud Rate Generation Freescale Semiconductor 319Spsck SPI Serial Clock Mosi Master Data Out, Slave DataMiso Master Data In, Slave Data Out SS Slave SelectModes of Operation SPI in Stop ModesSPI Control Register 1 SPIxC1 SPIxC1 Field DescriptionsMaster Mode Slave Mode SPI Control Register 2 SPIxC2SS Pin Function Modfen SsoeSPI Stop in Wait Mode SPI Baud Rate Register SPIxBRSPIxC2 Register Field Descriptions Modfen Bidiroe SpiswaiSPI Status Register SPIxS SPIxBR Register Field DescriptionsSppr SPRSPI Data Register SPIxD SPI Clock Formats 10. SPI Clock Formats Cpha = Freescale Semiconductor 327SPI Interrupts 11. SPI Clock Formats Cpha =Mode Fault Detection Freescale Semiconductor 329330 Freescale Semiconductor TPM Clock Gating Chapter Timer/Pulse-Width Modulator S08TPMV3Freescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor TPM Block Diagram Freescale Semiconductor 337Signal Description ExtclkExtclk External Clock Source TPMxCHn TPM Channel n I/O PinsFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TPM Status and Control Register TPMxSC TPMxSC Field DescriptionsTOF Toie Cpwms Clksb Clksa PS2 PS1 TOFTPM Counter Registers TPMxCNTHTPMxCNTL TPM-Clock-Source SelectionPrescale Factor Selection ClksbclksaTPM Counter Modulo Registers TPMxMODHTPMxMODL TPMxCNT158 Any write to TPMxCNTH clears the 16-bit counterTPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter Freescale Semiconductor 343TPM Channel n Status and Control Register TPMxCnSC TPMxMOD158TPMxMOD70 CHnF CHnIE MSnB MSnA ELSnB ELSnAMSnBMSnA ELSnBELSnA Mode Configuration TPMxCnSC Field DescriptionsMode, Edge, and Level Selection CpwmsTPM Channel Value Registers TPMxCnVHTPMxCnVL Mode, Edge, and Level SelectionTPMxCnV158 TPMxCnV70Counter Clock Source CounterFreescale Semiconductor 347 Counter Overflow and Modulo Reset TPM Clock Source SelectionChannel Mode Selection Manual Counter ResetInput Capture Mode Output Compare ModeEdge-Aligned PWM Mode 15. PWM Period and Pulse Width ELSnA=0Center-Aligned PWM Mode Freescale Semiconductor 351Description of Reset Operation Reset OverviewGeneral Timer Overflow Interrupt TOF Description Interrupt Local Source Description EnableDescription of Interrupt Operation Interrupt SummaryChannel Event Interrupt Description Center-Aligned PWM CaseChapter Version 1 ColdFire Debug CF1DEBUG Freescale Semiconductor 355Version 1 ColdFire Core CF1Core OEPPST Bkgd BDCModes of Operations Debug Revision SummaryRevision Csrhrl CSR2D1HRLBDM Command Types Command Type FlashCore Status Command Set BDM?Debug Module Signals Description External Signal DescriptionsBDM GO Debug Module Memory Map DRc Register Name Width Access Reset Value Section BitsCPU Configuration/Status Register CSR Bstat FOF TRG Halt Bkpt HRL BKD IPW CSR Field DescriptionsTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Xcsr Reference Summary Extended Configuration/Status Register XcsrMethod Reference Details CPU Cstat Halt Stop Eseqc Clksw SEC Erase Enbdm Apcsc ApceXcsr CPU StateSEC R Eseqc WErase W Configuration/Status Register 2 CSR2 CSR2 Reference SummaryXcsr CSR2 Syncpc IntervalCSR2 Field Descriptions PSTBWA7 Pstb Valid Data Locations Oldest to NewestConfiguration/Status Register 3 CSR3 10. CSR3 Reference SummaryPstbss Start Condition Stop ConditionBFC Bfcdiv DIV8 BDM Address Attribute Register BaarBFCDIV8 Address Attribute Trigger Register Aatr SZM TTM TMMSignal of the processor’s local bus BDM memory commands Normal processor access Else ReservedTrigger Definition Register TDR SZML2ED L2EAL2T L1T L1EAL2T Program Counter Breakpoint/Mask Registers PBR0-3, Pbmr Three bits disables the address breakpointNo inversion Invert data breakpoint comparators Mask Reset 15. PBR0 Field DescriptionsDRc 0x08 PBR0 DRc 0x09 PbmrAddress Breakpoint Registers ABLR, Abhr 17. Pbmr Field DescriptionsAbhr Ablr19. Abhr Field Description Data Breakpoint and Mask Registers DBR, Dbmr21. Dbmr Field Descriptions Background Debug Mode BDM 22. Access Size and Operand Data LocationAddress1 Access Size Operand Location Resulting Set of Possible Trigger CombinationsCPU Halt 23. CPU Halt SourcesHalt Source Halt Timing Description Cpucrard =Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details 15. BDC Host-to-Target Serial Bit Timing Freescale Semiconductor 38516. BDC Target-to-Host Serial Bit Timing Logic BDM Command Set Descriptions Freescale Semiconductor 387Miscellaneous Commands Memory CommandsCore Register Commands PST Trace Buffer Read Commands24. BDM Command Code Field Descriptions CRGCRG CRN VBRBDM Command Set Summary 25. BDM Command SummaryAckdisable AckenableReaddreg ReadcregReadpstb Syncpc WritecregDisable host/target handshake protocol Always Available Enable host/target handshake protocol Always Available0x03 Freescale Semiconductor 393Enter active background mode if enabled Non-intrusive 0x32 Host → Target Memory data7-0 Target → 0x36Data7-0 0x3A Memory0x33 Xcsrsb0x37 0x3B0x12 Memory data7-0 Target 0x16 Memory Data15-8 Memory data7-00x12 Memory Target → Host 0x16 MemoryNo operation Non-intrusive Read CPU control register Active BackgroundRead debug control register Non-intrusive 0xA0+CRN Host → Target Dreg data0x30 Address23-0 Target Memory data7-0 Target → Host0x31 0x350x39 0x50+CRN Host → Target Pstb dataRead general-purpose CPU register Active Background Read Xcsr Status Byte Always AvailableRead CSR2 Status Byte Always Available Read CSR3 Status Byte Always AvailableSynchronize PC to PST/DDATA Signals Non-intrusive Write CPU control register Active Background0xC0+CRN Creg data Freescale Semiconductor 401Write debug control register Non-intrusive 0x80+CRN Dreg data0x10 Address23-0 Memory Data7-0 Host → targetWrite general-purpose CPU register Active Background Serial Interface Hardware Handshake Protocol Write Xcsr Status Byte Always AvailableWrite CSR2 Status Byte Always Available Write CSR3 Status Byte Always Available19. Target Acknowledge Pulse ACK Freescale Semiconductor 405Hardware Handshake Abort Procedure 20. Handshake Protocol at Command Level21signal timing is not drawn to scale Freescale Semiconductor 40721. ACK Abort Procedure at the Command Level Real-Time Trace Support Real-Time Debug SupportFreescale Semiconductor 409 Enter user mode 26. Processor Status EncodingsPST40 Definition Instructions, generate different encodings0x08-0x0B Begin Execution of Taken Branch PST =Freescale Semiconductor 411 23. Example JMP Instruction Output in Pstb PST Values DescriptionPST Trace Buffer Pstb 18.4.3.3 PST/DDATA ExamplePstbpst PstbddataProcessor Status, Debug Data Definition 27. PST/DDATA Specification for User-Mode Instructions Instruction Operand SyntaxPST/DDATA Freescale Semiconductor 415416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set GND Reset Freescale-Recommended BDM PinoutNo Connect Freescale Semiconductor 419420 Freescale Semiconductor Appendix a Revision History Changes between Rev and RevMCF51QE128RM Rev to Rev Changes Chapter DescriptionRevision History Page How to Reach Us