ColdFire Core

 

Table 7-2. CCR Field Descriptions

 

 

Field

Description

 

 

7–5

Reserved, must be cleared.

 

 

4

Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified

X

result.

 

 

3

Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.

N

 

 

 

2

Zero condition code bit. Set if result equals zero; otherwise cleared.

Z

 

 

 

1

Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand

V

size; otherwise cleared.

 

 

0

Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a

C

subtraction; otherwise cleared.

 

 

7.2.5Program Counter (PC)

The PC contains the currently executing instruction address. During instruction execution and exception processing, the processor automatically increments contents of the PC or places a new value in the PC, as appropriate. The PC is a base address for PC-relative operand addressing.

The PC is initially loaded during reset exception processing with the contents of location 0x(00)00_0004.

BDM: Load: 0xEF (PC)

Store: 0xCF (PC)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

Access: User read/write BDM read/write

7

6

5

4

3

2

1

0

R

W

Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 7-6. Program Counter Register (PC)

7.2.6Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary.

In addition, because the V1 ColdFire core supports a 16 Mbyte address space, the upper byte of the VBR is also forced to zero. The VBR can be used to relocate the exception vector table from its default position in the flash memory (address 0x(00)00_0000) to the base of the RAM (address 0x(00)80_0000) if needed.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor

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Freescale Semiconductor MCF51QE128RM manual Program Counter PC, Vector Base Register VBR, CCR Field Descriptions