Freescale Semiconductor MCF51QE128RM Sync, Set PRDIV8 and clock divider fields in CSR3, Stop

Chapter 4 Memory

Secure state unknown/unpowered

Hold BKGD=0, apply power, wait N+16 cycles

for POR to deassert

Secure state unknown, CPU halted,

FEI 10 MHz clock, SYNC required

N = number of cycles for SIM to release internal reset. Adder of 16 imposed by ColdFire core.

BKGD=0 during reset ensures that ENBDM comes up ‘1’.

FLL enabled, internal reference (FEI) at 10MHz is reset default for the ICS.

SYNC

Secure state unknown, CPU halted,

FEI 10 MHz clock, synchronized to debugger

Read XCSR

XCSR[31:24] = 0x87

Set PRDIV8 and clock divider fields in CSR3

STOP

XCSR[31:24] ≠ 1000_01x1

XCSR[25] = 0

STOP Already unsecured

Error condition check code or device.

Write XCSR[31:24] = 0x87 to initiate

erase/verify of flash memory Note: This write is required

Is XCSR[25] cleared	No
(erase/verify complete)
?
Yes

On-chip flash is erased and unsecure

Write CSR2[25:24]=11 to initiate BDM reset to halt or write CSR2[25:24]=01 to initiate BDM reset to run

1 Delay ‘TBD’ cycles

Device is unsecure

1. The last three steps are optional, but recommended.

Ways to enter BDM halt mode:

1.BKGD=0 during POR

2.BKGD=0 during external reset

3.BKGD=0 during BDM reset

4.BFHBR=1 during BDM reset

5.Issue BACKGROUND command via BDM interface

6.HALT instruction

7.BDM breakpoint

8.ColdFire fault-on-fault

Of these, only method 1 is guaranteed to work under all circumstances because of the ability to program different functions on the BKGD package pin.

Figure 4-15. Procedure for Clearing Security on MCF51QE128/64/32 via the BDM Port

MCF51QE128 MCU Series Reference Manual, Rev. 3

92 Freescale Semiconductor

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